Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Proceedings ArticleDOI
Emerging technologies on silicon
TL;DR: This paper discusses long term evolutionary paths as well as some more disruptive approaches of the different building blocks of an information processing system, namely the processing unit, memory, interface and communication, and the interconnection of these elements, taking into account some of the expected fundamental and practical limits.
Patent
Integrated circuit having memory array including row redundancy, and method of programming, controlling and/or operating same
TL;DR: In this article, the present inventions are directed to such row redundancy circuitry, including address decoder circuitry to generate decoded row address data in response to an applied row address, a memory to store decoded redundant row addresses data, normal word line drivers, and redundancy address evaluation circuitry to determine whether the decoded data corresponds to the redundant row address.
Patent
Electronic device and method and performing logic functions
TL;DR: In this article, an electronic device is presented which is configured to operate as at least one logic gate, which comprises an electrodes arrangement of one or more basic units, the basic unit being configured to define at least 1 vacuum space for free charged particles' propagation and comprising an input assembly for supplying an input signal, and a floating electrode assembly accommodated proximal said input assembly and serving for reading an output signal therefrom.
Proceedings ArticleDOI
3-Dimensional Integration for Interconnect Reduction in for Nano-CMOS Technologies
TL;DR: The technology is based on highly scalable multi-gate MOSFET structures which are promising for nano-scale integration and the extension to have active devices placed the third dimension allow significant reduction in the interconnect loading.
Patent
Method of manufacturing semiconductor device
TL;DR: In this article, a first insulating film is formed over a substrate, and a second insulating layer is formed on the first layer by an isotropic etching process.