Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Patent
Temporary semiconductor structure bonding methods and related bonded semiconductor structures
Mariam Sadaka,Ionut Radu +1 more
TL;DR: In this paper, the authors propose implanting atom species into a carrier die or wafer to form a weakened region within the carrier die and then bonding the carrier to a semiconductor structure.
Patent
Semiconductor component having plate, stacked dice and conductive vias
Warren M. Farnworth,Alan G. Wood,William M. Hiatt,James M. Wark,David R. Hembree,Kyle K. Kirby,Pete A. Benson +6 more
TL;DR: A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die as mentioned in this paper, which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be attached to the back side of base die.
Journal ArticleDOI
Cascade single-chip phosphor-free white light-emitting diodes
TL;DR: In this article, a cascade single-chip phosphor-free white LED was proposed with GaAs∕GaN heterojunction direct wafer bonding, which demonstrated the CIE chromaticity coordinates of about (0.3, 0.3) at 20mA.
Proceedings Article
Automatic generation of breakpoint hardware for silicon debug
Vermeulen,Urfianto,Goel +2 more
Patent
Process for making a buried conductor by fusing two wafers
TL;DR: In this paper, the authors propose a process for bonding two wafers together to form a single wafer with a continuous interface, and for selectively burying a low impedance conductor in the wafer, by providing host and guest wafer having substantially the same crystal orientation and periodicity.