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Patent

System comprising a semiconductor device and structure

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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.
Abstract
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

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Patent

Magnetic cell structures, and methods of fabrication

TL;DR: In this article, the magnetic cell structure of a seed material including tantalum, platinum, and ruthenium is described, where the seed material comprises a platinum portion overlying a tantalum portion, and a ruthensium component overlying the platinum portion.
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Complementary metal oxide semiconductor (cmos) ultrasonic transducers and methods for forming the same

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Methods of manufacturing three-dimensional semiconductor devices

TL;DR: In this paper, the authors describe a three-dimensional semiconductor manufacturing process that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming another stack structure including a second opening exposing the sacrificial fill pattern, and then removing the first and second spacer.
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Integrated magnetic random access memory with logic device having low-k interconnects

TL;DR: In this paper, a substrate and a first upper dielectric layer over first, second and third regions of the substrate are provided, where the bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region.
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3D memory semiconductor device and structure

TL;DR: In this paper, a 3D memory device with side-gated logic transistors for controlling the memory is presented, where the first memory layer includes a first monolithically mono-crystal layer directly bonded to the second isolation layer, and the second memory transistor is self-aligned to the first one.
References
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Book

Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Journal ArticleDOI

Nanowire transistors without junctions

TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Journal ArticleDOI

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

Shekhar Borkar
- 01 Nov 2005 - 
TL;DR: This article discusses effects of variability in transistor performance and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
Patent

Three dimensional structure memory

TL;DR: The 3Dimensional Structure (3DS) Memory (100) as mentioned in this paper is a three-dimensional structure (3D) memory that allows physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized.
Patent

Transparent contacts for organic devices

TL;DR: In this paper, a multicolor organic light emitting device employs vertically stacked layers of double heterostructure devices which are fabricated from organic compounds, and the devices are configured as stacked to provide a staircase profile whereby each device is separated from the other by a thin transparent conductive contact layer to enable light emanating from each of the devices to pass through the semitransparent contacts and through the lower device structures.