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Patent

System comprising a semiconductor device and structure

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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.
Abstract
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

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Patent

Bipolar junction transistor and forming method thereof, and related integrated circuit

TL;DR: In this paper, a bipolar junction transistor (BJT) is provided, which includes a collector region that is disposed within a semiconductor substrate, and an emitter region, which is arranged within the collector region and within the base region.
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Three-dimensional semiconductor device and three-dimensional logic array structure thereof

Chen Shihong
TL;DR: In this paper, a three-dimensional semiconductor device and a 3D logic array structure thereof were described, which consists of an array structure, a peripheral circuit structure and the three dimensional logic array.
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Memory cell including vertical transistors and horizontal nanowire bit lines

TL;DR: In this paper, the authors describe a cell library consisting of a first transistor and a second transistor, and the first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure.
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System for and method of fabricating an integrated circuit

TL;DR: In this article, a method of fabricating an integrated circuit based on a via grid and a standard cell layout is presented. But the method is not suitable for the design of a single-input single-output (SIMO) circuit.
References
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Book

Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Journal ArticleDOI

Nanowire transistors without junctions

TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Journal ArticleDOI

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

Shekhar Borkar
- 01 Nov 2005 - 
TL;DR: This article discusses effects of variability in transistor performance and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
Patent

Three dimensional structure memory

TL;DR: The 3Dimensional Structure (3DS) Memory (100) as mentioned in this paper is a three-dimensional structure (3D) memory that allows physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized.
Patent

Transparent contacts for organic devices

TL;DR: In this paper, a multicolor organic light emitting device employs vertically stacked layers of double heterostructure devices which are fabricated from organic compounds, and the devices are configured as stacked to provide a staircase profile whereby each device is separated from the other by a thin transparent conductive contact layer to enable light emanating from each of the devices to pass through the semitransparent contacts and through the lower device structures.