Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
Reads0
Chats0
TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
Citations
More filters
Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
More filters
Journal ArticleDOI
Overview of transient liquid phase and partial transient liquid phase bonding
Grant O. Cook,Carl D. Sorensen +1 more
TL;DR: Partial transient liquid phase (PTLP) bonding as discussed by the authors is a variant of TLP bonding that is typically used to join ceramics and has found many applications, most notably the joining and repair of Ni-based superalloy components.
Patent
Three-dimensional read-only memory
TL;DR: A read-only memory structure, having a three dimensional arrangement of memory elements, is described in this paper, where memory elements are partitioned into multiple memory levels and each memory level is stacked on top of another.
Patent
Packaging of integrated circuits and vertical integration
TL;DR: In this paper, a first level packaging wafer (110) is made of a semiconductor or insulating material, and the bumps (150B) on the wafer are made using vertical integration technology, without solder or electroplating.
Patent
Customizable and programmable cell array
TL;DR: In this article, a customizable logic array including an array of programmable cells having a multiplicity of inputs and amultiplicity of outputs and customized interconnections providing permanent direct interconnection among at least a plurality of the multiplicity inputs and at least the plurality of outputs was described.
Patent
Color separation in an active pixel cell imaging array using a triple-well structure
TL;DR: In this paper, a preferred imaging array (102, 104, 106) is based upon a three-color pixel sensor using a triple-well structure (100), which results in elimination of color aliasing by measuring each of the three primary colors (RGB) in each pixel in the same location.