Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Patent
Three-dimensional integrated semiconductor devices
TL;DR: In this article, the authors describe a three-dimensional integration of semiconductor devices and a resulting device, which combines low temperature wafer bonding methods with backside/substrate contact processing methods, preferably with silicon on insulator devices.
Journal ArticleDOI
Beyond Moore's Law: the interconnect era
TL;DR: The nanoelectronics that follow silicon must be interconnect-centric, because this new technology will likely use "transistors" that approach, if not surpass, the 0.1 ps latency of 10 nm generation silicon transistors.
Patent
HIGH-k/METAL GATE MOSFET WITH REDUCED PARASITIC CAPACITANCE
TL;DR: In this article, a high-k gate dielectric/metal gate MOSFET with a reduced parasitic capacitance is presented, where the gate spacer is located upon an upper surface of both the gate and the highk gate.
Patent
Epitaxial SiOx barrier/insulation layer
TL;DR: In this article, a method for producing an insulating or barrier layer, useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects such that epitaxial silicon substantially free from defects can be deposited on said deposition layer.
Patent
Unipolar resistance random access memory (RRAM) device and vertically stacked architecture
TL;DR: In this article, a low-cost unipolar rewritable variable-resistance memory device, made of cross-point arrays of memory cells, vertically stacked on top of one another and compatible with a polycrystalline silicon diode, is presented.