Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Patent
Methods of forming semiconductor constructions
TL;DR: In this paper, the authors describe semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions, which can be incorporated into transistor devices, and can contain verticallyextending channel regions of the transistor devices.
Patent
Light emitting diode emitting red, green and blue light
TL;DR: In this article, a multicolor light emitting diode (MLED) is disclosed which can emit various different colored light at the same time, including red, green and blue.
Patent
Method for making a three-dimensional integrated circuit structure
TL;DR: In this paper, a plurality of vertically oriented semiconductor devices are added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures.
Journal ArticleDOI
Design for debug: catching design errors in digital chips
TL;DR: The system presented here consists of an on-chip debug infrastructure and supporting debugger software, which interacts with the infrastructure to make the chip's features accessible through a serial interface.
Proceedings ArticleDOI
Advances, challenges and opportunities in 3D CMOS sequential integration
Perrine Batude,Maud Vinet,Bernard Previtali,Claude Tabone,Cuiqin Xu,J. Mazurier,Olivier Weber,Francois Andrieu,L. Tosti,L. Brevard,Benoit Sklenard,Perceval Coudrain,Shashikanth Bobba,H. Ben Jamaa,P.-E. Gaillardon,A. Pouydebasque,Olivier P. Thomas,C. Le Royer,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Laurent Clavelier,G. De Micheli,Simon Deleonibus,O. Faynot,Thierry Poiroux +26 more
TL;DR: This paper addresses the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer and can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices.