Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Patent
Tri-gate devices and methods of fabrication
TL;DR: In this paper, a gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the SINR, which is a semiconductor device consisting of a top surface and laterally-opposite sidewalls formed on a substrate.
Patent
Methods and devices for fabricating and assembling printable semiconductor elements
Ralph G. Nuzzo,John A. Rogers,Etienne Menard,Keon Jae Lee,Dahl-Young Khang,Yugang Sun,Matthew Meitl,Zhengtao Zhu +7 more
TL;DR: In this article, the authors present methods and devices for fabricating printable semiconductor elements and assembling them onto substrate surfaces, which are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on polymeric materials.
Journal ArticleDOI
High-power AlGaInN flip-chip light-emitting diodes
Jonathan J. Wierer,Daniel A. Steigerwald,Michael R. Krames,J. O'Shea,M. J. Ludowise,G. Christenson,Y. C. Shen,C. H. Lowery,Paul S. Martin,S. Subramanya,W. Götz,Nathan F. Gardner,R. S. Kern,S. A. Stockman +13 more
TL;DR: In this article, the authors presented a flip-chip light-emitting diodes (FCLEDs) with a large emitting area (∼0.70 mm2) and an optimized contacting scheme allowing high current (200-1000 mA, J∼30-143 A/cm2) operation with low forward voltages.
Patent
Three-dimensional memory array and method of fabrication
N. Johan Knall,Mark G. Johnson +1 more
TL;DR: In this paper, a multi-level memory array employing rail-stacks is described, which include a conductor and semiconductor layers, separated by an insulating layer used to form antifuses.
Journal ArticleDOI
Depth from defocus: a spatial domain approach
Murali Subbarao,Gopal Surya +1 more
TL;DR: A new method named STM is described for determining distance of objects and rapid autofocusing of camera systems based on a new Spatial-Domain Convolution/Deconvolution Transform that requires only two images taken with different camera parameters such as lens position, focal length, and aperture diameter.