Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Patent
Buried via technology for three dimensional integrated circuits
TL;DR: In this article, a three-dimensional integrated circuit with a first and a second active circuit layers is proposed, where the metal layers are connected by metal inside a buried via, and the fabrication method includes etching a via in the first active circuit layer to expose the first metal layer and depositing metal inside the via.
Patent
Substrate processing apparatus
Masataka Ito,Kenji Yamagata,Yasuo Kakizaki,Kazuhito Takanashi,Hiroshi Miyabayashi,Ryuji Moriwaki,Takashi Tsuboi +6 more
TL;DR: In this paper, the SOI layer of a substrate is chemically etched by supplying a chemical solution to the substrate, and the film thickness of the etched SOI layers is measured, and when the measured film thickness has a predetermined value, a process of chemically etching the SoI layer ends.
Journal ArticleDOI
A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems
TL;DR: A high-sensitivity capacitive-coupling receiver is presented for wireless wafer probing systems that increases the communication distance by more than four times while providing tolerance against distance-voltage-area variations.
Patent
Semiconductor memory device with three-dimensional array and repair method thereof
Doo-gon Kim,Ki-Tae Park +1 more
TL;DR: In this paper, a nonvolatile memory device includes a three-dimensional (3D) cell array, a column selection circuit and a fuse block, which is used to repair defective columns with one of multiple redundant bit lines located in the 3D cell array.
Patent
Thermally induced phase switch for laser thermal processing
TL;DR: In this paper, a phase switch layer is used to control the amount of heat transferred to a process region from exposure with a pulse of radiation, which may be in the form of a scanning beam.