Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
Reads0
Chats0
TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
Citations
More filters
Patent
Electronic device including a nonvolatile memory structure having an antifuse component and a process of forming the same
TL;DR: In this paper, a nonvolatile memory cell can be programmed by flowing current through the antifuse component and the switch and bypassing the current away from the read transistor.
Patent
Method of Forming Layout Design
Tung-Heng Hsieh,Lin Chung-Te,Sheng-Hsiung Wang,Hui-Zhong Zhuang,Min-Hsiung Chiang,Chiang Ting-Wei,Li-Chun Tien +6 more
TL;DR: In this article, a method of forming a layout design for fabricating an integrated circuit (IC) is disclosed, which includes identifying one or more areas in the layout design occupied by one or many segments of a plurality of gate structure layout patterns.
Patent
Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors
TL;DR: The gated transistors may include a gate along the base region and spaced from the base regions by dielectric material, with the gate not overlapping either the B-C junction or B-E junction.
Patent
Replacement contacts for all-around contacts
Guy M. Cohen,Michael A. Guillorn +1 more
TL;DR: In this paper, a method of forming contacts to source and drain regions in a FET device includes the following steps: a patternable dielectric is deposited onto the device so as to surround each of the source and Drain regions.
Patent
Method for fabricating finFET with merged fins and vertical silicide
Veeraraghavan S. Basker,Andres Bryant,Huiming Bu,Wilfried Haensch,Effendi Leobandung,Chung-Hsun Lin,Theodorus E. Standaert,Tenko Yamashita,Chun-Chen Yeh +8 more
TL;DR: In this article, a method for fabricating a finFET device is described, where fin structures include a semiconductor layer and extend in a first direction, and a gate stack is formed on the BOX layer over the fin structures and extending in a second direction.
References
More filters
Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Journal ArticleDOI
Nanowire transistors without junctions
Jean-Pierre Colinge,Chi-Woo Lee,Aryan Afzalian,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Pedram Razavi,B. O'Neill,Alan Blake,Mary White,Anne-Marie Kelleher,Brendan McCarthy,Richard Murphy +13 more
TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Journal ArticleDOI
Designing reliable systems from unreliable components: the challenges of transistor variability and degradation
TL;DR: This article discusses effects of variability in transistor performance and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
Patent
Three dimensional structure memory
TL;DR: The 3Dimensional Structure (3DS) Memory (100) as mentioned in this paper is a three-dimensional structure (3D) memory that allows physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized.
Patent
Transparent contacts for organic devices
TL;DR: In this paper, a multicolor organic light emitting device employs vertically stacked layers of double heterostructure devices which are fabricated from organic compounds, and the devices are configured as stacked to provide a staircase profile whereby each device is separated from the other by a thin transparent conductive contact layer to enable light emanating from each of the devices to pass through the semitransparent contacts and through the lower device structures.