Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Patent
Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process
TL;DR: In this article, a method for manufacturing a semiconductor device having an alignment feature is presented, in which an n-type dopant is inserted into a substrate to form an implanted region and an unimplanted region in the substrate.
CMOS transistor processing compatible with monolithic 3-D integration
Bipin Rajendran,R. S. Shenoy,D. J. Witte,N. S. Chokshi,R. L. DeLeon,G. S. Tompa,Roger Fabian W. Pease +6 more
Patent
Method of fabricating semiconductor wafer
TL;DR: In this article, a method of fabricating a semiconductor wafer is presented, which includes preparing a substrate wafer having a non-single-crystalline thin layer, disposing at least one single crystalline pattern adjacent to the non-Single-Crystal-Thick-Layer (SLC) layer on the substrate, and forming a material layer contacting the single crystaline pattern on the SLC layer.
Patent
Through substrate via semiconductor components
Hans-Joachim Barth,Jens Pohl +1 more
TL;DR: In this paper, a structure and method of forming landing pads for through substrate vias in forming stacked semiconductor components are described. And the landing pad structures that include multiple levels of conductive plates connected by vias such that the electrical connection between a through substrate etch and landing pad is independent of the location of the bottom of the through substrate trench.
Patent
Automatic trace determination method and apparatus for automatically determining optimal trace positions on substrate using computation
TL;DR: In this paper, an automatic trace determination apparatus for automatically determining optimal positions of traces from pads to corresponding vias on a substrate using computation comprises tentative determination means for tentatively determining a tentative target line with which tentative positions of bending points of traces are aligned; and final determination means by correcting the tentative target lines so that at least clearances between the adjacent traces and between the traces and vias adjacent to the corresponding traces can be secured.