Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Proceedings ArticleDOI
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
Kaizad Mistry,C. Allen,C. Auth,B. Beattie,Daniel B. Bergstrom,M. Bost,M. Brazier,M. Buehler,Annalisa Cappellani,R. Chau,C. H. Choi,G. Ding,K. Fischer,Tahir Ghani,R. Grover,W. Han,D. Hanken,M. Hattendorf,J. He,J. Hicks,R. Huessner,D. Ingerly,Pulkit Jain,R. James,L. Jong,Subhash M. Joshi,C. Kenyon,K. Kuhn,K. Lee,Huichu Liu,J. Maiz,B. Mclntyre,P. Moon,J. Neirynck,S. Pae,C. Parker,D. Parsons,Chetan Prasad,L. Pipes,M. Prince,Pushkar Ranade,T. Reynolds,J. Sandford,Lucian Shifren,J. Sebastian,J. Seiple,D. Simon,Swaminathan Sivakumar,Pete Smith,C. Thomas,T. Troeger,P. Vandervoorn,S. Williams,K. Zawadzki +53 more
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Journal ArticleDOI
Introduction to flash memory
TL;DR: The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible and an insight into the multilevel approach, where two bits are stored in the same cell, is presented.
Journal ArticleDOI
Junctionless multigate field-effect transistor
Chi-Woo Lee,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Jean-Pierre Colinge +5 more
TL;DR: In this article, the authors describe a metaloxide-semiconductor MOS transistor concept in which there are no junctions and the channel doping is equal in concentration and type to the source and drain extension doping.
Patent
Process for the production of thin semiconductor material films
TL;DR: In this paper, the process for the preparation of thin moncrystalline or polycrystaline semiconductor material films, characterized in that it comprises subjecting a semiconductor materials wafer having a planar face to the three following stages: a first stage of implantation by bombardment by ions creating in the volume of said wafer a layer (3) of gaseous microbubbles defining in the volumetric volume a lower region (6) constituting the mass of the substrate and an upper region (5) constituing the thin film, a second stage
Journal ArticleDOI
Demystifying 3D ICs: the pros and cons of going vertical
W.R. Davis,John W. Wilson,S. Mick,Jian Xu,Hao Hua,C. Mineo,A.M. Sule,Michael B. Steer,Paul D. Franzon +8 more
TL;DR: In this paper, the authors present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule.