Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Patent
Semiconductor manufacturing using modular substrates
TL;DR: A manufacturing method using a modular substrate-based processing scheme for producing semiconductor devices, provides multiple modular processing units which may be arranged together to form any of various cohesive processing units or individually or sequentially processed through standard semiconductor processing equipment.
Patent
Diffusionless conductor/oxide semiconductor field effect transistor and methods for making and using the same
TL;DR: A diffusionless field effect transistor is formed at a face of a semiconductor layer (12) of a first conductivity type and includes a source conductor (36), a drain conductor (38) and a channel region (44) as mentioned in this paper.
Patent
Methods of manufacturing a three-dimensional semiconductor device and semiconductor devices fabricated thereby
TL;DR: In this article, a heat conductive plug is used to channel heat away from devices on a substrate, while high temperature processes are performed on a stacked semiconductor layer, which can then be used to fabricate improved thin film transistors.
Patent
Electronic components and method of fabricating the same
TL;DR: In this paper, a method for fabricating integrated electronic components is described, in which an initial structure is produced on the surface of a first substrate, and at least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the one substrate.
Patent
Charge trapping memory cell
TL;DR: In this article, the erasure occurs by Fowler-Nordheim tunneling of the electrons through the lower boundary layer to source or drain or through the upper boundary layer into the gate electrode.