Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Journal ArticleDOI
A Study of the CMP Effect on the Quality of Thin Silicon Films Crystallized by Using the ??-Czochralski Process
Patent
Thin film semiconductor device and fabrication method therefor
TL;DR: In this article, a relaying pad is formed in a predetermined portion in an insulation layer of the single-crystal thin film device, in a region where the single crystal thin-film device is formed.
Patent
Method of manufacturing semiconductor device
TL;DR: In this paper, an insulating film is placed beneath the alignment mark in structure; an alignment mark consisting of said multi-layered film comprising an alignment marking layer and the insulating layer, which constitutes a stepped part with an increased difference in level, is first formed, inside a mark hole, in a manner of self-alignment; and then the metal film which is the very cause of the above problem is formed thereon.
Patent
Method and on-chip control apparatus for enhancing process reliability and process variability through 3d integration
TL;DR: In this paper, a method and on-chip controller for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional integration applied to electronic packaging is presented, along with an onchip reliability/variability controller arrangement for implementing the inventive method.
Patent
Semiconductor device, production method thereof, and display device
TL;DR: In this article, the authors presented a semiconductor device including a pixel part and an integrated circuit part on a substrate, the pixel part including a switching element having a gate electrode formed on semiconductor thin film.