Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Self-repair logic for stacked memory architecture
TL;DR: In this paper, self-repair logic for stacked memory architectures is proposed for the repair of operation of a defective TSV of the plurality of data TSVs, including utilization of the one or more spare TSVs.
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Novel 3D Integration Method Using SOI Substrates And Structures Produced Thereby
Sampath Purushothaman,Roy Yu +1 more
TL;DR: In this article, a process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer of a top silicon Wafer comprising a silicon-on-insulator (SOI) wafer.
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Junctionless nanowire transistors for 3d monolithic integration of cmos inverters
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References
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Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Journal ArticleDOI
Nanowire transistors without junctions
Jean-Pierre Colinge,Chi-Woo Lee,Aryan Afzalian,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Pedram Razavi,B. O'Neill,Alan Blake,Mary White,Anne-Marie Kelleher,Brendan McCarthy,Richard Murphy +13 more
TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Journal ArticleDOI
Designing reliable systems from unreliable components: the challenges of transistor variability and degradation
TL;DR: This article discusses effects of variability in transistor performance and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
Patent
Three dimensional structure memory
TL;DR: The 3Dimensional Structure (3DS) Memory (100) as mentioned in this paper is a three-dimensional structure (3D) memory that allows physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized.
Patent
Transparent contacts for organic devices
TL;DR: In this paper, a multicolor organic light emitting device employs vertically stacked layers of double heterostructure devices which are fabricated from organic compounds, and the devices are configured as stacked to provide a staircase profile whereby each device is separated from the other by a thin transparent conductive contact layer to enable light emanating from each of the devices to pass through the semitransparent contacts and through the lower device structures.