Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
Reads0
Chats0
TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
Citations
More filters
Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
More filters
Patent
Cell architecture to reduce customization in a semiconductor device
TL;DR: In this paper, the logic cells in the device including at least two three-input look-up tables, one two-input lookup table and a flip-flop are connected so that any lookup table can drive at least one input of any other look up table.
Proceedings ArticleDOI
Engineered substrates for future More Moore and More than Moore integrated devices
Laurent Clavelier,Chrystel Deguet,L. Di Cioccio,E. Augendre,A. Brugere,P. Gueguen,Y. Le Tiec,Hubert Moriceau,Marc Rabarot,Thomas Signamarcheix,Julie Widiez,O. Faynot,Francois Andrieu,Olivier Weber,C. Le Royer,Perrine Batude,Louis Hutin,J.-F. Damlencourt,Simon Deleonibus,Emmanuel Defay +19 more
TL;DR: The Smart Cut technology was used to fabricate Silicon On Insulator (SOI) substrates as mentioned in this paper, which is a mature product and is focused on the integration of new materials and functionalities in order to improve device performances and enlarge the application spectrum.
Patent
Metrology system and method for stacked wafer alignment
Travis Eiles,Shriram Ramanathan +1 more
TL;DR: In this paper, an infrared radiation source and an infrared camera are positioned on opposing sides of a stacked wafer to determine if stacked wafers are in proper alignment, and the degree of alignment of the wafer can be measured using the fiducial marks exposed in the image.
Proceedings ArticleDOI
A high-performance stacked-CMOS SRAM cell by solid phase growth technique
TL;DR: In this article, a stacked-CMOS SRAM cell with a polysilicon p-channel thin-film transistor (TFT) load has been proposed, achieving a leakage-current of 0.07 pA/mm and an on/off ratio of 105 at the logic swing of 3 V. The high performance has been attained as a result of enlarging the grain size for the active region of the p-ch TFT by a novel solid phase growth (SPG) technique.
Proceedings ArticleDOI
NiSi Schottky Barrier Process-Strained Si (SB-PSS) CMOS Technology for High Performance Applications
Chih-Hsin Ko,Hung-Wei Chen,T.J. Wang,T. Kuan,J. Hsu,Chien-Chao Huang,Chung-Hu Ge,L. Lai,Wen-Chin Lee +8 more
TL;DR: In this article, the Schottky-barrier (SB)-based process-strained Si (PSS) technology with single-NiSi source/drain (S/D) and ultra-thin gate oxide of 1.2 nm is demonstrated for Lgate down to 39 nm.