Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Patent
Method of recovering alignment marks after chemical mechanical polishing of tungsten
Tsu Shih,Chen-Hua Yu +1 more
TL;DR: In this paper, the alignment marks are formed by filling alignment lines, formed in the dielectric when the contact holes are formed, with barrier metal and contact metal at the same time.
Patent
Method for fabricating a MOSFET device
TL;DR: In this paper, a MOSFET fabrication method capable of forming an ultra shallow junction while ensuring stability in controlling threshold voltage is presented, which relies on the use of a sacrificial gate structure to form LDD regions and the addition of side wall spacers to form source/drain regions, followed by the deposition of an interlayer insulating film.
Journal ArticleDOI
Nano-graphoepitaxy of semiconductors for 3D integration
F. Crnogorac,D. J. Witte,Qiangfei Xia,Bipin Rajendran,D. S. Pickard,Zhi Liu,Apurva Mehta,Shashank Sharma,Amir A. Yasseri,Theodore I. Kamins,Stephen Y. Chou,Roger Fabian W. Pease +11 more
TL;DR: In this paper, a surface relief grating of 190nm was used to mediate single crystal formation while continuous wave (CW) heating a thin film of amorphous silicon; the term "graphoepitaxy" was coined.
Patent
Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states
TL;DR: In this article, a method for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is described, and the relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R.
Patent
Resistive memory devices having a not-and(nand) structure
Matthew J. Breitwisch,Gary S. Ditlow,Michele M. Franceschini,Luis A. Lastras-Montano,Robert K. Montoye,Bipin Rajendran +5 more
TL;DR: In this article, the memory element access device is connected in parallel to the resistive memory element, which is used to control access to the memory elements in a not-and (NAND) structure.