Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
Citations
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Journal ArticleDOI
Overlay as the key to drive wafer scale 3D integration
Steven E. Steen,Douglas Charles Latulipe,Anna W. Topol,David J. Frank,Kevin Belote,Dominick Posillico +5 more
TL;DR: It is shown that controlled process integration enables significant reduction of the alignment errors between two substrates and drives the full potential of 3DIC.
Journal ArticleDOI
Low-temperature fabrication and characterization of Ge-on-insulator structures
TL;DR: In this article, the defect density of a Ge-on-insulator detector was found to increase with decreasing bonding temperature, indicating that defects caused by hydrogen implantation are passivated more effectively.
Patent
Method of forming an electronic device using a separation-enhancing species
Leo Mathew,Dharmesh Jawarani +1 more
TL;DR: In this article, a method of forming an electronic device can include forming a metallic layer by an electrochemical process over a side of a substrate that includes a semiconductor material, which can also include introducing a separation-enhancing species into the substrate at a distance from the side, and separating the semiconductor layer and the metallic layer from the substrate.
Proceedings ArticleDOI
Setting up 3D sequential integration for back-illuminated CMOS image sensors with highly miniaturized pixels with low temperature fully depleted SOI transistors
P. Coudrain,Perrine Batude,X. Gagnard,C. Leyris,S. Ricq,Maud Vinet,A. Pouydebasque,N. Moussy,Yvon Cazaux,B. Giffard,P. Magnan,Pascal Ancey +11 more
TL;DR: In this article, back-illuminated photodiodes are realized on a first silicon layer, while readout transistors are located on a second silicon layer for low noise pixel performances.
Proceedings ArticleDOI
3D monolithic integration
Perrine Batude,Maud Vinet,A. Pouydebasque,C. Le Royer,Bernard Previtali,Claude Tabone,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Alain Toffoli,F. Allain,V. Mazzocchi,D. Lafond,Simon Deleonibus,O. Faynot +15 more
TL;DR: A 3D monolithic process flow relying on molecular wafer bonding is proposed and results in all critical steps are given and functional top and bottom transistors as well as 3D structures such as invertors and SRAMs are demonstrated.