Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Proceedings ArticleDOI
Fabrication and packaging of microbump interconnections for 3D TSV
TL;DR: The developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies are highlighted and various reliability tests were carried out for mechanical characterization of microbump interconnections.
Patent
Electrically programmable link structures and methods of making same
TL;DR: In this article, the authors described a method for fabricating electrically programmable link structures by fabricating a first conductor, which comprises a refractory conductive material, then fabricating an insulative link material over the first conductor.
Patent
Semiconductor substrates having useful and transfer layers
Bruno Ghyselen,Fabrice Letertre +1 more
TL;DR: In this paper, a semiconductor substrate that includes a relatively thin monocrystalline useful layer, an intermediate layer transferred from a source substrate, and a relatively thick layer of a support present on one of the useful layers of the intermediate layer.
Patent
Memory chip and semiconductor device using the memory chip and manufacturing method of those
TL;DR: In this article, a memory chip including four basic chips F is cut out of the wafer and a dicing line is interposed between F configuring the memory chip, F can change word organization by a control signal individually.
Carrier techniques for thin wafer processing
TL;DR: In this article, three different types of carrier techniques have been investigated and developed: thermal release tapes, solvable thermoplastic glue layer and mobile electrostatic carrier, which were applied for manufacture of ultra-thin RFID chips, 12 µm thin CMOS image sensors and to a new process sequence that enables the formation of solder balls at the front side of an already thinned device wafer.