Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Patent
Method of making an adaptive configurable gate array
TL;DR: In this paper, a configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined.
Patent
Three-Dimensional System-in-Package Architecture
Oscar M. K. Law,Kuo H. Wu +1 more
TL;DR: In this paper, a system and method for making semiconductor die connections with through-silicon vias (TSVs) is described, which is used to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies.
Patent
Semiconductor structure comprising active zones
TL;DR: In this article, a multi-wavelength diode with active zones is proposed, where a first active zone (AZ1) is grown on a surface of the substrate (SUB), whereby one or several further active zones (AZ 1 - Azn) are epitaxially grown one on the other and the active zones are serially connected from the lower active zone to an upper active zone by means of tunnel diodes (TD1 - TDn), serving as low-impedance resistors.
Patent
Method of fabrication of a torsional micro-mechanical mirror system
Robert William McClelland,Noa M. Rensing,Mark Bradley Spitzer,P. D. Aquilino,Paul M. Zavracky +4 more
TL;DR: A torsional micro-mechanical mirror system as mentioned in this paper includes a mirror assembly rotatably supported by a torsion mirror support assembly for rotational movement over and within a cavity in a base.
Patent
Silicon-compatible surface plasmon optical elements
TL;DR: In this article, a waveguide based on an ultra-long-range surface plasmon (ULRSP) waveguide mode was proposed for Si-compatible electro-optic devices.