Showing papers on "Silicon on insulator published in 2013"

Hybrid Silicon Photonic Integrated Circuit Technology

Abstract: In this paper, we review the current status of the hybrid silicon photonic integration platform with emphasis on its prospects for increased integration complexity. The hybrid silicon platform is maturing fast as increasingly complex circuits are reported with tens of integrated components including on-chip lasers. It is shown that this platform is well positioned and holds great potential to address future needs for medium-scale photonic integrated circuits.

Polarization management for silicon photonic integrated circuits

Abstract: Polarization management is very important for photonic integrated circuits (PICs) and their applications. Due to geometrical anisotropy and fabrication inaccuracies, the characteristics of the guided transverse-electrical (TE) and transverse-magnetic (TM) modes are generally different. Polarization-dependent dispersion and polarization-dependent loss are such manifestations in PICs. These issues become more severe in high index contrast structures such as nanophotonic waveguides made of silicon-on-insulator (SOI), which has been regarded as a good platform for optical interconnects because of the compatibility with CMOS processing. Recently, polarization division multiplexing (PDM) with coherent detection using silicon photonics has also attracted much attention. This trend further highlights the importance of polarization management in silicon PICs. The authors review their work on polarization management for silicon PICs using the polarization independence and polarization diversity methods. Polarization issues and solutions in PICs made of SOI nanowires and ridge waveguides are discussed.

Materials and Fabrication Processes for Transient and Bioresorbable High-Performance Electronics

Abstract: Materials and fabrication procedures are described for bioresorbable transistors and simple integrated circuits, in which the key processing steps occur on silicon wafer substrates, in schemes compatible with methods used in conventional microelectronics. The approach relies on an unusual type of silicon on insulator wafer to yield devices that exploit ultrathin sheets of monocrystalline silicon for the semiconductor, thin films of magnesium for the electrodes and interconnects, silicon dioxide and magnesium oxide for the dielectrics, and silk for the substrates. A range of component examples with detailed measurements of their electrical characteristics and dissolution properties illustrate the capabilities. In vivo toxicity tests demonstrate biocompatibility in sub-dermal implants. The results have significance for broad classes of water-soluble, “transient” electronic devices.

Ultralow loss single layer submicron silicon waveguide crossing for SOI optical interconnect

Abstract: We demonstrate compact, broadband, ultralow loss silicon waveguide crossings operating at 1550 nm and 1310 nm. Cross-wafer measurement of 30 dies shows transmission insertion loss of − 0.028 ± 0.009 dB for the 1550 nm device and − 0.017 ± 0.005 dB for the 1310 nm device. Both crossings show crosstalk lower than − 37 dB. The devices were fabricated in a CMOS-compatible process using 248 nm optical lithography with a single etch step.

Demonstration of a heterogeneously integrated III-V/SOI single wavelength tunable laser

Abstract: A heterogeneously integrated III-V-on-silicon laser is reported, integrating a III-V gain section, a silicon ring resonator for wavelength selection and two silicon Bragg grating reflectors as back and front mirrors. Single wavelength operation with a side mode suppression ratio higher than 45 dB is obtained. An output power up to 10 mW at 20 °C and a thermo-optic wavelength tuning range of 8 nm are achieved. The laser linewidth is found to be 1.7 MHz.

Ultra-thin DVS-BCB adhesive bonding of III-V wafers, dies and multiple dies to a patterned silicon-on-insulator substrate

Abstract: Heterogeneous integration of III-V semiconductor materials on a silicon-on-insulator (SOI) platform has recently emerged as one of the most promising methods for the fabrication of active photonic devices in silicon photonics. For this integration, it is essential to have a reliable and robust bonding procedure, which also provides a uniform and ultra-thin bonding layer for an effective optical coupling between III-V active layers and SOI waveguides. A new process for bonding of III-V dies to processed silicon-on-insulator waveguide circuits using divinylsiloxane-bis-benzocyclobutene (DVS-BCB) was developed using a commercial wafer bonder. This “cold bonding” method significantly simplifies the bonding preparation for machine-based bonding both for die and wafer-scale bonding. High-quality bonding, with ultra-thin bonding layers (<50 nm) is demonstrated, which is suitable for the fabrication of heterogeneously integrated photonic devices, specifically hybrid III-V/Si lasers.

Advances in silicon carbide science and technology at the micro- and nanoscales

Abstract: Advances in silicon carbide microfabrication and growth process optimization for silicon carbide nanostructures are ushering in new opportunities for microdevices capable of operation in a variety of demanding applications, involving high temperature, radiation, or corrosive environment. This review focuses on the materials science and processing technologies for silicon carbide thin films and low dimensional structures, and details recent progress in manufacturing technology, including deposition, metallization, and fabrication of semiconductor microdevices, with emphasis on sensor technology. The challenges remaining in developing silicon carbide as a mainstay materials platform are discussed throughout.

Nanoscale plasmonic memristor with optical readout functionality.

Abstract: We experimentally demonstrate for the first time a nanoscale resistive random access memory (RRAM) electronic device integrated with a plasmonic waveguide providing the functionality of optical readout. The device fabrication is based on silicon on insulator CMOS compatible approach of local oxidation of silicon, which enables the realization of RRAM and low optical loss channel photonic waveguide at the same fabrication step. This plasmonic device operates at telecom wavelength of 1.55 μm and can be used to optically read the logic state of a memory by measuring two distinct levels of optical transmission. The experimental characterization of the device shows optical bistable behavior between these levels of transmission in addition to well-defined hysteresis. We attribute the changes in the optical transmission to the creation of a nanoscale absorbing and scattering metallic filament in the amorphous silicon layer, where the plasmonic mode resides.

Integrated high-quality factor silicon-on-sapphire ring resonators for the mid-infrared

Abstract: We demonstrate high-quality (Q) factor grating-coupled ring resonators in a silicon-on-sapphire platform, operating at wavelengths between 4.3 and 4.6 μm. Total Q-factors of 151 000 and intrinsic Q-factors of 278 000 are measured, representing the highest Q-factors measured at the mid-infrared in Si.

Silicon-on-nitride waveguides for mid- and near-infrared integrated photonics

Abstract: Silicon-on-nitride ridge waveguides are demonstrated and characterized at mid- and near-infrared optical wavelengths. Silicon-on-nitride thin films were achieved by bonding a silicon handling die to a silicon-on-insulator die coated with a low-stress silicon nitride layer. Subsequent removal of the silicon-on-insulator substrate results in a thin film of silicon on a nitride bottom cladding, readily available for waveguide fabrication. At the mid-infrared wavelength of 3.39 μm, the fabricated waveguides have a propagation loss of 5.2 ± 0.6 dB/cm and 5.1 ± 0.6 dB/cm for the transverse-electric and transverse-magnetic modes, respectively.

Demonstration of silicon-on-insulator mid-infrared spectrometers operating at 3.8 um

Abstract: The design and characterization of silicon-on-insulator mid- infrared spectrometers operating at 3.8µm is reported. The devices are fabricated on 200mm SOI wafers in a CMOS pilot line. Both arrayed waveguide grating structures and planar concave grating structures were designed and tested. Low insertion loss (1.5-2.5dB) and good crosstalk characteristics (15-20dB) are demonstrated, together with waveguide propagation losses in the range of 3 to 6dB/cm.

2×2 adiabatic 3-dB coupler on silicon-on-insulator rib waveguides

Abstract: We demonstrated 2×2 broadband adiabatic 3-dB couplers based on silicon rib waveguides. Functioning as 50/50 optical power splitters, these devices can be used in optoelectronic applications. Fabricated using siliconon-insulator technology, we demonstrated the performance of the adiabatic 3-dB couplers by integrating two couplers into an unbalanced Mach-Zehnder Interferometer (MZI). Measurements of the MZI were made over a 100 nm wavelength range. Extinction ratios in excess of 33.4 dB were obtained over the wavelength range from 1520 nm to 1600 nm, for light injected into Input Port1 and measured at Output Port2, i.e., the cross port response.

Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

Abstract: The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

From the Casimir Limit to Phononic Crystals: 20 Years of Phonon Transport Studies Using Silicon-on-Insulator Technology

Abstract: Silicon-on-insulator (SOI) technology has sparked advances in semiconductor and MEMs manufacturing and revolutionized our ability to study phonon transport phenomena by providing single-crystal silicon layers with thickness down to a few tens of nanometers. These nearly perfect crystalline silicon layers are an ideal platform for studying ballistic phonon transport and the coupling of boundary scattering with other mechanisms, including impurities and periodic pores. Early studies showed clear evidence of the size effect on thermal conduction due to phonon boundary scattering in films down to 20 nm thick and provided the first compelling room temperature evidence for the Casimir limit at room temperature. More recent studies on ultrathin films and periodically porous thin films are exploring the possibility of phonon dispersion modifications in confined geometries and porous films. [DOI: 10.1115/1.4023577]

A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications

Abstract: Recently Silicon Photonics has generated an outstanding interest for integrated optical communications. In this paper we describe a 300mm Silicon Photonics platform designed for 25Gb/s and above applications at the three typical communication wavelengths and compatible with 3D integration. Main process features and device results are described.

CMOS compatible horizontal nanoplasmonic slot waveguides TE-pass polarizer on silicon-on-insulator platform

Abstract: An ultra-compact broadband TE-pass polarizer was proposed and demonstrated on the silicon-on-insulator (SOI) platform, using the horizontal nanoplasmonic slot waveguide (HNSW). Detailed design principle was presented, taking advantage of the distinct confinement region of the TE and TM modes in the HNSW. TM mode cut-off could be achieved when waveguide width was below 210 nm. Proof-of-concept devices were subsequently fabricated in a CMOS-compatible process. The optimized device had an active region length of 1 μm, three orders of magnitude smaller than similar device previously demonstrated on the SOI platform. More than 16 dB polarization extinction ratio was achieved across 80 nm wavelength range, with a relatively low insertion loss of 2.2dB. The compact device size and excellent broadband performance could provide a simple yet satisfactory solution to the polarization dependent performance drawback of the silicon photonics devices on the SOI platform.

Silicon-organic hybrid (SOH) IQ modulator using the linear electro-optic effect for transmitting 16QAM at 112 Gbit/s

Abstract: Advanced modulation formats call for suitable IQ modulators. Using the silicon-on-insulator (SOI) platform we exploit the linear electro-optic effect by functionalizing a photonic integrated circuit with an organic χ(2)-nonlinear cladding. We demonstrate that this silicon-organic hybrid (SOH) technology allows the fabrication of IQ modulators for generating 16QAM signals with data rates up to 112 Gbit/s. To the best of our knowledge, this is the highest single-polarization data rate achieved so far with a silicon-integrated modulator. We found an energy consumption of 640 fJ/bit.

Silicon-on-insulator spectrometers with integrated GaInAsSb photodiodes for wide-band spectroscopy from 1510 to 2300 nm.

Abstract: We present a silicon-on-insulator (SOI) based spectrometer platform for a wide operational wavelength range. Both planar concave grating (PCG, also known as echelle grating) and arrayed waveguide grating (AWG) spectrometer designs are explored for operation in the short-wave infrared. In addition, a total of four planar concave gratings are designed to cover parts of the wavelength range from 1510 to 2300 nm. These passive wavelength demultiplexers are combined with GaInAsSb photodiodes. These photodiodes are heterogeneously integrated on SOI with benzocyclobutene (DVS-BCB) as an adhesive bonding layer. The uniformity of the photodiode characteristics and high processing yield, indicate a robust fabrication process. We demonstrate good performance of the miniature spectrometers over all operational wavelengths which paves the way to on-chip absorption spectroscopy in this wavelength range.

Revisited parameter extraction methodology for electrical characterization of junctionless transistors

Abstract: Several electrical parameters characterize device performance, electron transport and doping level in MOS transistors. In this paper, Junctionless Transistors (JLTs) fabricated on (100) silicon on insulator (SOI) wafer with 145 nm thick BOX and 9 nm silicon thickness were considered. Parameter extraction methodologies were revisited in order to account for the unique electrical properties of JLT devices. The deduced parameters, such as threshold voltage, flat-band voltage, drain induced barrier lowering (DIBL), low field mobility and channel doping level, are shown to reveal the specific features of JLT compared to conventional inversion-mode transistors.

Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs

Abstract: This paper analyzes the 2-D short-channel effect in ultrathin SOI MOSFETs. An empirical, channel length-dependent scale length is extracted from the lateral field slope of a series of numerically simulated devices. We show how this scale length is related to the short-channel threshold voltage roll-off and minimum channel length with and without a substrate bias. The benefit of a reverse substrate bias is investigated and understood in terms of the field and distribution of inversion charge in the silicon film. In particular, how a bulk-like short-channel effect is achieved when an accumulation layer is formed at the back surface. Furthermore, the effect of a high-κ gate insulator is studied and scaling implications discussed.

Stimulated and spontaneous four-wave mixing in silicon-on-insulator coupled photonic wire nano-cavities

Abstract: We report on four-wave mixing in coupled photonic crystal nano-cavities on a silicon-on-insulator platform. Three photonic wire cavities are side-coupled to obtain three modes equally separated in energy. The structure is designed to be self-filtering, and we show that the pump is rejected by almost two orders of magnitude. We study both the stimulated and the spontaneous four-wave mixing processes: owing to the small modal volume, we find that signal and idler photons are generated with a hundred-fold increase in efficiency as compared to silicon micro-ring resonators.

Circuits, devices, methods and combinations related to silicon-on-insulator based radio-frequency switches

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system typically includes a plurality of field- effect transistors (FETs) connected in series between first and second nodes, with each FET having a gate, a source, a drain and a body. Disclosed are, among others, various examples of circuits that couple different portions of a FET and/or different FETs to yield desirable performance improvements for RF switch systems. In some embodiments, one or more features of a given example can provide such performance improvements. In some embodiments, features from different examples can be combined to yield such performance improvements.

Vertical super-thin body semiconductor on dielectric wall devices and methods of their fabrication

Abstract: The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices.

Vertical integration of high-Q silicon nitride microresonators into silicon-on-insulator platform.

Abstract: We demonstrate a vertical integration of high-Q silicon nitride microresonators into the silicon-on-insulator platform for applications at the telecommunication wavelengths. Low-loss silicon nitride films with a thickness of 400 nm are successfully grown, enabling compact silicon nitride microresonators with ultra-high intrinsic Qs (~ 6 × 10(6) for 60 μm radius and ~ 2 × 10(7) for 240 μm radius). The coupling between the silicon nitride microresonator and the underneath silicon waveguide is based on evanescent coupling with silicon dioxide as buffer. Selective coupling to a desired radial mode of the silicon nitride microresonator is also achievable using a pulley coupling scheme. In this work, a 60-μm-radius silicon nitride microresonator has been successfully integrated into the silicon-on-insulator platform, showing a single-mode operation with an intrinsic Q of 2 × 10(6).

Role of Joule Heating on Current Saturation and Transient Behavior of Graphene Transistors

Abstract: We use simulations to examine current saturation in sub-micron graphene transistors on SiO2/Si. We find that self-heating is partly responsible for current saturation (lower output conductance) but degrades current densities above 1 bmA/μm by up to 15%. Heating effects are reduced if the supporting insulator is thinned or, in shorter channel devices, by partial heat sinking at the contacts. The transient behavior of such devices has thermal time constants of ~ 30-300 ns, which is dominated by the thickness of the supporting insulator and that of the device capping layers (a behavior also expected in ultrathin-body SOI transistors). The results shed important physical insight into the high-field and transient behavior of graphene transistors.

CMOS-Compatible Integrated Spectrometer Based on Echelle Diffraction Grating and MSM Photodetector Array

Abstract: We demonstrate an integrated spectrometer-on-a-chip composed of an echelle diffraction grating (EDG) and metal-semiconductor-metal (MSM) waveguide photodetector array based on silicon-on-insulator (SOI). In the passive section, silicon oxynitride (SiON) is chosen as the material for the waveguide core and is deposited after selectively removing the top silicon layer of the SOI wafer. The buried silicon dioxide layer of the SOI wafer functions as the lower cladding for the SiON core waveguide. In the active section, the MSM photodetector array is fabricated on the top silicon layer of the SOI waveguide with a pitch width of 7.5 μm. With the butt-coupling structure, a responsivity of 0.41 A/W is obtained at 850 nm. Based on the CMOS-compatible fabrication process, we have fabricated a 60-channel spectrometer with a chip size of 9 mm × 6 mm operating around 850 nm. The measured channel spacing is 0.494 nm, with an adjacent channel crosstalk around 18 dB. The channel nonuniformity is less than 1.5 dB. The CMOS-compatible spectrometer with integrated silicon photodetector array can provide a low-cost solution for high-resolution on-chip spectral analysis for visible and near-infrared light with the wavelength below 1100 nm.

Back-End Deposited Silicon Photonics for Monolithic Integration on CMOS

Abstract: We present the vision of back-end deposited silicon photonics (BDSP) and review works that have been done in this field. Individual aspects of BDSP platform including excimer-laser-annealed polycrystalline silicon, low-loss plasma-enhanced chemical vapor deposition silicon nitride waveguide, modulator, detector, electrical interface, back-end CMOS compatibility, and benefits of the platform are discussed in detail.

Low loss 40 Gbit/s silicon modulator based on interleaved junctions and fabricated on 300 mm SOI wafers

Abstract: We demonstrate high-speed silicon modulators based on carrier depletion in interleaved pn junctions fabricated on 300mm-SOI wafers using CMOS foundry facilities. 950µm-long Mach Zehnder (MZ) and ring resonator (RR) modulator with a 100µm radius, were designed, fabricated and characterized. 40 Gbit/s data transmission has been demonstrated for both devices. The MZ modulator exhibited a high extinction ratio of 7.9 dB with only 4 dB on-chip losses at the operating point.

Silicon and silicon germanium nanowire formation

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.