Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Process for thinning the active silicon layer of a substrate of "silicon on insulator" (soi) type

Abstract: The invention relates to a process for thinning the active silicon layer (2) of a substrate, which comprises an insulator layer (4) between active layer (2) and a support (3), this process comprising one step of sacrificial thinning of active layer (2) by formation of a sacrificial oxide layer (20) by sacrificial thermal oxidation and deoxidation of, layer (20). The process is noteworthy in that it comprises: a step of forming a complementary oxide layer (5), on said active layer (2), using an oxidizing plasma, this layer (5) having a thickness profile complementary to that of oxide layer (20), so that the sum of the thicknesses of the layer (5) and of the sacrificial silicon oxide layer (20) are constant over the surface of the treated substrate, a step of deoxidation of this layer (5), so as to thin active layer (2) by a uniform thickness.

Semiconductor structures including bonding layers, multi-junction photovoltaic cells and related methods

Abstract: A method of fabricating a semiconductor structure includes the formation of a first bonding layer at least substantially comprised of a first III-V material on major a surface of a first element, and formation of a second bonding layer at least substantially comprised of a second III-V material on a major surface of a second element. The first bonding layer and the second bonding layer are disposed between the first element and the second element, and the first element and the second element are attached to one another at a bonding interface disposed between the first bonding layer and the second bonding layer. Semiconductor structures are fabricated using such methods.

Method for dissolving a silicon dioxide layer

Abstract: This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface thereof, a supporting substrate, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in a furnace in which structures are supported on a support, the dissolution method resulting in the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products, and the furnace including traps suitable for reacting with the volatile products, so as to reduce the concentration gradient of the volatile products parallel to the front surface of at least one structure.

Engineered Substrates for Advanced CMOS Technology Nodes and More-Than-Moore Applications

Abstract: Traditional planar bulk or partially depleted SOI (PDSOI) CMOS transistor architectures at present leading edge of miniaturization are plagued by limitations due to unacceptably high current leakages and variability. To cope with these intrinsic limitations there is a need to introduce innovative technologies which take advantage of the benefits of Fully Depleted (FD) devices. There are two main architectures for the undoped channel FD device: 3D FinFETs (SOI or bulk-based) and 2D FDSOI-based transistors. Both of them are being introduced in high volume manufacturing (HVM). A pioneer of SOI concept, silicon on sapphire (SOS) substrates, have recently entered a mainstream radio frequency (RF) application market. Other flavors of engineered substrates, e.g. for photonics or 3D-based applications, have moved from research to industrial development phase. In this work an overview of the recent advances in the development of the engineered substrates for More Moore and More-than-Moore applications will be presented.

Soi finfet with reduced fin width dependence

Abstract: The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor.