Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Method for making a composite substrate and composite substrate according to the method

Abstract: The present invention provides methods for fabricating a composite substrate including a supporting substrate and a layer of a binary or ternary material having a crystal form that is non-cubic and semi-polar or non-polar. The methods comprise transferring the layer of a binary or ternary material from a donor substrate to a receiving substrate.

Hydrogen implantation-induced defects in bulk Si studied by Raman spectrometry

Abstract: Ion implantation is a subject of interest because it is widely used in the semiconductor industry, to modify the carrier density in a transistor channel region and to enable splitting in the wafer bonding process. In the case of SOI wafers produced by SmartCut™, the implantation of light ions creates only a small amount of damage in the materials. Thus, H-implanted Si remains crystalline and only small changes are observed in physical properties as compared to non-implanted silicon crystal. However, as energy is applied to the system, by heating for example, H-implanted Si undergoes extreme stress eventually breaking the crystal. We have investigated the changes in the Si crystal during this process using Raman spectroscopy. Examining the slight shift and enlargement of the phonon peak and applying the spatial correlation model characterized defects. We could extract a phonon correlation length L, the shorter the L value, the larger the amount of defects. Variations due to H concentration (implantation depth profile relative to the surface) were investigated by using different excitation wavelengths (probe depths of 20–500 nm). Samples were also thinned by etching so that the defect density could be measured with fixed excitation energy (fixed probe depth). Finally, we draw the variation of L. All results were compared to the vacancy profiles simulated with the binary collision code IMSIL. Good agreement was obtained between the defect profiles estimated by both methods.

Novel low temperature 3D wafer stacking technology for high density device integration

Abstract: Low temperature 3D wafer stacking for very high density device integration is achieved using the Smart Cut™ technology and solid phase re-crystallization. Thin silicon PN bi-layers of high quality are transferred onto new handle substrate without exceeding 500°C. The current-voltage characteristics of the intrinsic PN diode are significantly improved by using low temperature solid-phase epitaxial re-growth process in combination with the Smart Cut™ technology. An original process integration scheme is described in order to minimize the diode leakage.

LP MOCVD growth of InAlN/GaN HEMT heterostructure : comparison of sapphire, bulk SiC and composite SiCopSiC substrates for HEMT device applications

Abstract: In this paper we report on low-pressure metalorganic vapour deposition of InAlN/GaN heterostructures grown on different substrates (Sapphire, bulk SiC, composite SiCopSiC) for HEMT applications, and on first device performances obtained with these heterostructures. Optimisation of the crystal growth on each kind of substrate has led to InAlN/GaN HEMT heterostructures grown on bulk SiC and on composite SiCopSiC substrates which are successfully compared, in terms of material quality, to the standard GaAlN/GaN HEMT heterostructures grown on bulk SiC substrates. First devices based on InAlN/GaN heterostructures grown on bulk SiC exhibit very good microwave performances, with output power of 10.3 W/mm at 10 GHz, similar to those obtained with GaAlN/GaN heterostructures, confirming the promising potential of InAlN material. (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)