Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Manufacture of structure equipped with semiconductor material on substrate

Abstract: PROBLEM TO BE SOLVED: To separate/divide a structure from a donor substrate, in which the structure such as an LED, a laser diode or the like is formed, in good yield and low cost. SOLUTION: The donor substrate and a receiver substrate are prepared, and the receiver substrate comprises one or more motifs on the front surface by relief, furthermore, the donor substrate is combined with the receiver substrate in the motif. A frangible region exists in the donor substrate at a designated depth, and a thin layer is prepared between the frangible region and a joint interface. This method keeps a combination between the motif and the donor substrate, and peels off a portion of the thin layer which locates in each motif from the donor substrate by generating fracture in the frangible region and a thickness of the thin layer, then gives energy in order to make the peeled portion be the structure. COPYRIGHT: (C)2006,JPO&NCIPI

Method for producing a single-crystal film of aln material and substrate for the epitaxial growth of a single-crystal film of aln material

Abstract: A process for producing a monocrystalline layer of AlN material comprises the transfer of a monocrystalline seed layer of SiC-6H material to a carrier substrate of silicon material, followed by the epitaxial growth of the monocrystalline layer of AlN material.

A simple test structure for the electrical characterization of front and back channels for advanced SOI technology development

Abstract: Pseudo-MOSFET delivers a fast, simple and reliable way of characterizing electrically SOI substrates without the need of full CMOS fabrication. However, the information refers to the back interface. Here, to probe the front interface, we extend the concept to a double-gate pseudo-MOSFET. The structure provides a pertinent test vehicle for the characterization and development of transistors channel and gate stack materials in a configuration similar to fully fabricated transistors. We show that the devices with undoped terminals need specialized modeling development to describe the double gate effect. Devices with doped terminals are immediately exploitable for parameter extraction.

Semiconductor structures including stacks of indium gallium nitride layers

Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.

Layout engineering to suppress hysteresis of negative capacitance FinFET

Abstract: Negative capacitance (NC), which arises from two energy minima of ferroelectric material, is proposed as one of the solutions for the next generation CMOS technology. However, the side-effect (i.e., hysteresis in current-vs.-voltage characteristic) of NC FinFET should be minimized, especially for being adopted as CMOS logic devices. If the capacitance matching between the ferroelectric capacitor and the dielectric capacitor in NC FinFET is satisfied, hysteresis-free and steep switching features can be obtained. In this work, the hysteresis in current-vs.-voltage characteristic is suppressed by lowering the capacitance value of FinFET (i.e., using the layout engineering for FinFET): While the hysteresis of NC FinFET was decreased, the performance degradation was negligible.