Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Device for splitting substrat with obstacle detection means

Abstract: The invention relates to a device (1) for splitting a substrate (2), said substrate comprising two adjoining wafers defining between them a cleavage plane, said device comprising - a base (11), - means (12) for splitting substrate wafers, - means for performing controlled displacement of some substrate wafers (2) comprising at least one pusher (5) mobile relative to the base (11) of the device (1) comprising handling means for substrates, said handling means being adapted to accommodate substrates in a reception space of substrates (2) on the pusher (5), said pusher (5) being capable of displacing substrates (2) arranged in a support (8), the device comprising detection means (9) adapted to determine the absence or the presence of obstacles inside at least one region of the reception space of the pusher (5) when the pusher (5) is in a detection position, said region being located near the handling means for substrates.

Trapping of implanted hydrogen for ultrathin layer transfer

Abstract: We have studied the impact of the incorporation of a buried and ultrathin layer (i.e a few nm), engineered to trap the implanted hydrogen in the donor substrate, on the silicon layer transfer by Smart Cut™. Two kinds of buried layers were studied: boron doped silicon and silicon-germanium alloy. We show that thin layers of boron doped silicon are particularly efficient to trap implanted hydrogen from the surrounding matrix. Using this structure, the transferred silicon layer presents typically a roughness of a few angstroms RMS, which represents an order of magnitude lower than the process without trapping layer. Moreover, this approach allows to transfer ultrathin silicon layer, i.e less than 100 nm thick, and is then promising for advanced generation of Silicon-On-Insulator wafers.

Methods of forming semiconductor structures

Abstract: The present disclosure relates to a process for the manufacture of a high resistivity semiconductor substrate, comprising the following stages: providing a first substrate with an in-depth weakened layer; providing a second substrate with a layer of an oxide at the surface; attaching the first substrate to the second substrate so as to form a compound substrate comprising a layer of buried oxide; and cleaving the compound substrate at the level of the weakened layer. The process additionally comprises at least one stage of stabilization, in particular, a stabilization heat treatment, of the second substrate with the layer of oxide before the stage of cleaving at the level of the weakened layer.

Strained Silicon-on-Insulator Platform for Cointegration of Logic and RF—Part I: Implant-Induced Strain Relaxation

Abstract: The relaxation of tensile strain in fully depleted (FD) strained silicon-on-insulator (SSOI) by means of ion implantation is experimentally demonstrated in this work. This could enable SiGe p-channel field-effect transistors (pFETs) with high compressive strain (after ion implantation and Ge condensation) to be formed together with Si n-channel field-effect transistors (nFETs) with high tensile strain on the same substrate. From simulations in advanced technology node, 0.8% strain of nFETs and −0.9% strain of pFETs in fin structures can provide saturation drain current and peak ${G}_{\text {m}}$ enhancements of ~20%–30%. ${f}_{\text {T}}$ and ${f}_{\text {max}}$ benefit greatly from strain across the entire range of ${V}_{\text {G}}$ , with their peak values increasing significantly, thus allowing SSOI devices to meet 5G targets. In addition, forward back-bias shifts ${f}_{\text {T}}$ and ${f}_{\text {max}}$ curves toward lower $\boldsymbol \vert {V}_{\text {G}}\boldsymbol \vert $ , enabling reduced power consumption at the same high performance and providing better linearity. Hence, the ability to form highly strained nFETs and pFETs together on a common FD-SSOI substrate paves the way for it to become the ultimate high-performance complementary metal-oxide-semiconductor (CMOS) platform for 5G RF and logic circuits. The relaxation of the tensile strain is demonstrated and documented in Part I. A novel Comb-like device architecture to further enhance the SSOI electrical and RF performance is provided in Part II.