Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Random and channeling stopping power of H in Si below 100 keV

Abstract: Range profiles of H in Si, implanted in random and channeling directions at 10, 40 and 100 keV, are determined by SIMS and are used to calibrate an analytical model of electronic stopping implemented in our binary collision simulator IMSIL. The fitted random stopping power is within 6% of the latest versions of the stopping powers of Paul ( http://www.exphys.uni-linz.ac.at/Stopping ) and of SRIM ( http://www.srim.org ). The electronic energy loss in the center of the widest channel in Si, the [1 1 0] channel, is only slightly lower than in random direction, the maximum difference being 13% at the stopping power maximum. The precise shape of the range profiles of H channeled along [1 1 0] can only be reproduced by assuming a significantly higher electronic energy loss straggling than proposed in the literature.

A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration

Abstract: We demonstrate for the first time the feasibility of split C – V measurements on as-fabricated SOI wafers using pseudo-MOSFET configuration. An adapted methodology to determine the effective mobility of electrons and holes by split C – V technique is proposed and validated through comparison with the effective mobility extracted from static measurements. The method has been applied to different SOI materials (thin and thick film/BOX, passivated and non-passivated surface). The frequency and substrate depletion effects and the role of probe pressure and spacing are discussed. The electron mobility can exceed 500 cm 2 V −1 s −1 in thin SOI films with passivated surface.

Fabrication of highly reflecting epitaxy-ready Si-SiO/sub 2/ Bragg reflectors

Abstract: A complementary metal-oxide-semiconductor-compatible process for fabrication of highly reflecting Si-SiO/sub 2/ Bragg mirrors with a crystalline top layer was developed. It comprises only one step of wafer-bonding and allows for subsequent epitaxial growth on the mirror. A six-pair reflector centered at 1400 nm with a 99% bandwidth of 700 nm and a surface roughness of 0.136 nm is demonstrated.

On the origin of the mobility reduction in bulk-Si, UTBOX-FDSOI and SiGe devices with ultrathin-EOT dielectrics

Abstract: The effects of ultrathin EOT on the carrier mobility in bulk-Si, UTBOX-FDSOI and SiGe-QW pFET devices were compared. The mobility is found to decrease dramatically with the EOT (T inv ) as a result of stronger charge and surface roughness scattering at thinner SiO x interface layers irrespective of the device technology. UTBOX-FDSOI and bulk-Si nFETs have identical mobility values (190 cm2/Vs) at T inv =12.5A. In the UTBOX-FDSOI device architecture, a positive back gate bias provides a strong enhancement in electron mobility. In SiGe-QW pFET devices, a 150% improvement in hole-mobility is observed with low thermal budget laser-anneal (LA).

X-radiation response of SIMOX buried oxides: influence of the fabrication process

Abstract: X-ray induced electron and hole trapping properties have been investigated in SIMOX buried oxides of different processes, including standard and supplemental implantation oxides, as well as new thin and ultra-thin oxides. The effect of the substrate bias applied during irradiation is studied, and then used to extract both hole and electron trapping parameters. The results demonstrate that varying the oxygen implantation conditions has very little effect on the radiation induced behavior of the material. They show that the charge trapping properties of the buried oxide are related to the ultra high temperature anneal performed on the confined oxide layer, and confirm that the post implantation anneal is the most critical part of the SIMOX process.