Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Formation of III-V Semiconductor Engineered Substrates Using Smart CutTM Layer Transfer Technology

Abstract: Engineered substrates are expected to play a dominant role in the field of modern nano-electronic and optoelectronic technologies. For example, engineered substrates like SOI (Silicon On Insulator) make possible efficient optimization of transistors' current drive while minimizing the leakage and reducing parasitic elements, thus enhancing the overall IC performance in terms of speed or power consumption. Other generations of engineered substrates like strained SOI (sSOI) provide solutions to traditional scaling for 32 nm node and beyond [1] technologies. The Smart Cuta technology, introduced in the mid 1990's by M. Bruel [2] is a revolutionnary and powerful thin film technology for bringing to industrial maturity engineered substrate solutions. It is a combination of wafer bonding and layer transfer via the use of ion implantation. It allows multiple high quality transfers of thin layers, from a single crystal donor wafer onto another substrate of a different nature, allowing the integration of dissimilar materials. As a consequence, it opens the path to the formation of III-V based engineered substrates by integrating, for example, materials like GaAs [3], InP [4], SiC [5], GaN [6], Germanium [7] ,and Si [8 ]on a silicon, poly SiC, sapphire, ceramic, or metal substrates? In this paper, we will review the current wafer bonding and layer transfer technologies with a special emphasis on the Smart Cut technology applied to compound semiconductors. Beyond SOI, the innovation provided by substrate engineering will be illustrated by the case of Silicon and SiC engineered substrate serving as a platform for GaN and related alloys processing [9,10,11,12] as well as the case of Germanium/Si platform for the growth of GaAs/InP materials, opening the path to Si CMOS and III-V microelectronics/ optoelectronics functions hybrid integration [13, 14]. Recent results obtained in these two focused areas will be presented to emphasize the added functionalities offered by engineered substrates. [1] B. Ghyselen et al., ICSI3 proc., 173 5 (2003) [2] M. Bruel et al., Electron. Lett., vol 31, p. 1201 (1995) [3] E. Jalaguier et al., Electron. Lett., 34(4), 408 (1998) [4] E. Jalaguier et al. Proc. llth Intern. Conf. on InP and Related Materials, Davos, Switzerland, (1999) [5] L. Di Cioccio et al., Mat. Sci. and Eng. B Vol. 46, p. 349 (1997) [6] A. Tauzin and al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 119-127 [7] F. Letertre, et al. MRS Symp. Proc., 809, B4.4 (2004). [8] B. Faure et al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 106-118 [9] H. Lareche et al., Mat. Sci. For., Vols. 457–460 pp.. 1621 – 1624 (2004) [10] G. Meneghesso et al , IEDM 2007, to be published [11] Y. Dikme et al., Journal of Crystal Growth, v.272 (1-4), pp. 500-505 (2004) [12] J. Dorsaz and al., Proceedings, ICNS6 (2005) [13] S.G. Thomas et al., IEEE EDL Vol. 26, July 2005. [14] K. Chilukuri, Semi. Sci. Technol. 22 (2007) 29-34

Progress and challenges in the direct monolithic integration of III–V devices and Si CMOS on silicon substrates

Abstract: We present results on the direct monolithic integration of III–V devices and Si CMOS on a silicon substrate. Through optimization of device fabrication and material growth processes III–V devices with electrical performance comparable to devices grown on native III–V substrates were grown directly in windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices Engineered Substrates). While the results presented here are for InP HBTs, our direct heterogeneously integration approach is equally applicable to other III–V electronic (FETs, HEMTs) and opto-electronic (photodiodes, VSCLS) devices and opens the door to a new class of highly integrated, high performance, mixed signal circuits.

Implanted selective emitter solar cells by laser thermal annealing

Abstract: We investigated two innovative ways of processing implanted selective emitter structure, both allowing a precise control of dopant concentrations and profiles. After a full sheet phosphorus implantation step, the first process combines a line-shaped laser thermal annealing with a selective wet etching between crystalline and amorphous silicon to create a selective emitter. We studied the influence of the fluence of a nanosecond range pulsed laser (515 nm) on the emitter sheet resistance for various etching times. Solar cells passivation improvements were achieved with a gain in voltage and current as compared to the homogeneous emitter. In a second time, we investigated an advanced process for process simplification using a low implantation dose and a picosecond quasi-continuous wave laser emitting at 355nm wavelength to increase the junction depth under metallization. The phosphorus activation and concentration profile were studied for various laser power and laser irradiation rate.

300 mm ultra thin SOI material using Smart-Cut/sup /spl reg// technology

Abstract: We discuss a new ultra thin 300 mm SOI material, Unibond/sup (R)/, which fulfills industry requirements in terms of uniformity, quality and availability.

Method of bonding by molecular bonding

Abstract: A method of bonding by molecular bonding between at least one lower wafer (20) and an upper wafer (30) comprises positioning the upper wafer on the lower wafer. In accordance with the invention, a contact force (F) is applied to the peripheral side (22, 32) of at least one of the two wafers (30, 20) in order to initiate a bonding wave between the two wafers.