Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Methods for forming group iii-nitride materials and structures formed by such methods

Abstract: Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer.

Low temperature diffusion of impurities in hydrogen implanted silicon

Abstract: The effect of hydrogen implantation on the transport of impurities in silicon is studied. We use secondary ion mass spectrometry measurements to investigate the depth redistribution of oxygen, carbon, and fluorine during low temperature, ≤450 °C, isothermal anneals. Their fast migration toward the projected range region of H implants points to the existence of a strong interaction of the impurities with H-induced defects. Significantly enhanced, as compared to the literature values, diffusivities of the investigated impurities were obtained. The results reveal that hydrogen implantation can be advantageously used for the impurity profile engineering and gettering studies in silicon in the low temperatures annealing regime.

Advanced thermally compensated surface acoustic wave device and fabrication method

Abstract: The present invention relates to a method of fabrication of a surface acoustic wave device (20) comprising the step (a) of providing a piezoelectric structure (200), the step (b) of providing a dielectric structure, wherein the step (b) comprises a step (b1) of metalizing (S22) the dielectric structure (220, 221), and the method further comprising the step (c) of bonding (S24) the metalized dielectric structure (231) to the piezoelectric structure (200).

Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat

Abstract: L'invention concerne un procede d'obtention concomitante d'au moins une paire de structures (51,52) comprenant chacune une couche utile (110,120) reportee sur un substrat (71,2).Ce procede est remarquable en ce qu'il comprend les etapes consistant a :a) preparer une structure de rang 1 comprenant une couche utile reportee sur un substrat support (2),b) former une zone de fragilisation a l'interieur de ladite couche utile, de facon a y definir une couche utile avant (110) et une couche utile arriere (120),c) faire adherer un substrat raidisseur (71) sur la ladite couche utile avant (110),d) proceder au detachement de l'empilement de couches le long de la zone de fragilisation, pour obtenir deux structures de rang 2, la premiere (51) comprenant ledit substrat support (2) et ladite couche utile arriere (120) et la seconde (52) comprenant ledit substrat raidisseur (71) et ladite couche utile avant (110).Applications dans les domaines de l'electronique, l'optoelectronique ou l'optique.

Method for fabricating a semiconductor on insulator substrate with reduced SECCO defect density

Abstract: The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cm2 the implanting is carried out with a dose of less than 2.3×106 atoms per cm2 and the thinning is an oxidation step conducted at a temperature of less than 925° C.