Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

Abstract: For the first time, we report high performance hybrid channel ETSOI CMOS by integrating strained SiGe-channel (cSiGe) PFET with Si-channel NFET at 22nm groundrules. We demonstrate a record high speed ring oscillator (fan-out = 3) with delay of 8.5 ps/stage and 11.2 ps/stage at V DD = 0.9V and V DD = 0.7V, respectively, outperforming state-of-the-art finFET results. A novel “STI-last” integration scheme is developed to improve cSiGe uniformity and enable ultra high performance PFET with narrow widths. Furthermore, cSiGe modulates device V t , thus providing an additional knob to enable multi-V t while maintaining undoped channels for all devices.

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Abstract: In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

Highly uniform and low-loss passive silicon photonics devices using a 300mm CMOS platform

Abstract: Using an advanced 300mm CMOS-platform, we report record-low and highly-uniform propagation loss: 0.45±0.12dB/cm for wires, and 2dB/cm for slot waveguides. For WDM devices, we demonstrate channel variation(3-σ) within-wafer and within-device of 6.1nm and 1.2nm respectively.

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

Abstract: We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET) Competitive effective current (Ieff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (Ioff) of 100nA/μm and Vdd of 09V Excellent electrostatics is obtained, demonstrating the scalability of these devices to14nm and beyond Very low AVt (13mV·μm) of channel SiGe (cSiGe) PFET devices is reported for the first time BTI was improved >20% vs a comparable bulk device and evidence of continued scalability beyond 14nm is provided

Four-junction wafer bonded concentrator solar cells

Abstract: The highest solar cell conversion efficiencies are achieved with Four-junction devices under concentrated sunlight illumination. Different cell architectures are under development, all targeting an ideal bandgap combination close to 1.9 eV, 1.4 eV, 1.0 eV and 0.7 eV. Wafer bonding is used in this work to combine materials with a significant lattice-mismatch. Three cell architectures are presented using the same two top junctions of GaInP/GaAs but different infrared absorbers based on Germanium, GaSb or GaInAs on InP. The modelled efficiency potential at 500 suns is in the range of 49–54 % for all three devices but the highest efficiency is expected for the InP-based cell. An efficiency of 46 % at 508-suns was already measured by AIST in Japan for a GaInP/GaAs//GaInAsP/GaInAs solar cell and represents the highest independently confirmed efficiency today. Solar cells on Ge and GaSb are in the development phase at Fraunhofer ISE and first demonstration of functional devices is presented in this paper.