Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Process of making a semiconductor structure on a substrate

Abstract: A semiconductor entity is produced by supplying sufficient energy to detach a portion of a thin layer from a donor substrate located at a motif and to rupture bonds within the thin layer. The energy is insufficient to rupture the bond at the bonding interface. Production of a semiconductor entity involves providing a donor substrate (10) having a zone of weakness (15) at a predetermined depth to define a thin layer. The donor substrate includes a bonding interface. A receiver substrate (20) that includes at least one motif (22) on its surface is provided. The donor substrate is bonded at the bonding interface to the motif on the receiver substrate. Sufficient energy is supplied to detach a portion of the thin layer from the donor substrate located at the motif and to rupture bonds within the thin layer to form the semiconductor entity. The energy is insufficient to rupture the bond at the bonding interface. An independent claim is also included for a wafer comprising a first substrate including at least one projecting motif, and a second substrate bonded to the projecting motif. The second substrate further comprises a zone of weakness that defines a thin layer.

Multi-junctions in a semiconductor device formed by different deposition techniques

Abstract: A semiconductor device, in particular a solar cell is formed on the basis of a hybrid deposition strategy using MOCVD and MBE in order to provide lattice matched semiconductor compounds. To this end, the MBE may be applied for providing a nitrogen-containing semiconductor compound that allows a desired low band gap energy and a lattice matched configuration with respect to gallium arsenide substrates.

Enabling UTBB Strained SOI Platform for Co-integration of Logic and RF: Implant-Induced Strain Relaxation and Comb-like Device Architecture

Abstract: For the first time, ion implant was used to partially relax the tensile strain by half in the fully-depleted (FD) strained SOI (SSOl) so that SiGe pFETs with a higher compressive strain can be realized at a fixed Ge composition. This enables the co-integration of highly tensile-strained Si nFETs and compressive-strained SiGe pFETs on the same substrate, achieving significant improvement in electrical performance over the unstrained counterpart verified by both experiment and simulation results. We also propose a Comb-like strained SOI architecture to further boost RF performance, demonstrating peak $G_{\mathrm{m}}$ improved by 47% over unstrained n-type FinFET SOI, as well as an improvement of 22% and 36% for $f_{\mathrm{T}}$ and $f_{\max}$ , respectively, over n-type FinFETs SSOI.

Advances in the pseudo-MOSFET characterization method

Abstract: Silicon-on-Insulator wafers with two probe contacts on the top silicon film act as MOS transistors. This configuration called pseudo-MOSFET is largely used for characterization of material parameters such as mobility of carriers and interface quality. Thinner films or oxides induce stronger electrostatic coupling of surface and interface with the channel. We discuss new developments in the pseudo-MOSFET measurement related to the influence of these phenomena as well as the quality of the contacts on the film. Moreover the pseudo-MOS transistor proves to be highly sensitive to its free surface which opens the road to applications in the sensing field.

In Situ Characterization of Bias Instability in Bare SOI Wafers by Pseudo-MOSFET Technique

Abstract: Bias instability is a reliability issue affecting the electrical characteristics of a MOS transistor when the gate is stressed with relatively high voltage. For the first time, we characterize the instability of bare SOI wafers using the pseudo-MOSFET technique. The effect of positive and negative stress pulses on the properties of both hole and electron channels is systematically investigated using measure-stress-measure and on-the-fly methods. The origin of the instability, the dependence of the degradation with time, and the recovery after the stress are discussed.