Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods

Abstract: Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.

III-V layer transfer onto silicon and applications

Abstract: Integration of GaAs and InP with Si technology presents a huge potential interest. When realised, it will combine the superior electrical and optical properties of GaAs and InP with the mechanical and economical advantages of Si, including large integration density. To obtain such hybrid structures, heteroepitaxial growth has been investigated extensively but, up to now, the resulting devices have limited performance due to a high density of threading dislocations. Bonding technologies have also been developed and III-V optical devices on Si have been already demonstrated. In this paper, we review the application of the Smart Cut technology which allows large diameter GaAs (or InP) thin film to be transferred onto a full silicon (handle) wafer. This technique is fully compatible with the requirements of microelectronics manufacturing and, both, HEMTs and P-HEMTs structures have been realised. They exhibit electrical characteristics in close comparison to the prototype structures directly grown on a conventional GaAs or InP substrate.

Work-function engineering in gate first technology for multi-V T dual-gate FDSOI CMOS on UTBOX

Abstract: For the first time, we demonstrate low-V T (V Tlin ±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-V T pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500µA/µm I ON and 245µA/µm I EFF at 2nA/µm I OFF and V DD =0.9V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different V T from 0.32V to 0.6V for both nMOS and pMOS, demonstrating a real multiple-V T capability for FDSOI CMOS while keeping the channel undoped and the V T variability around A VT =1.3mV.µm.

Power-Dependent Raman Analysis of Highly Strained Si Nanobridges

Abstract: Strain analysis of complex three-dimensional nanobridges conducted via Raman spectroscopy requires careful experimentation and data analysis supported by simulations. A method combining micro-Raman spectroscopy with finite element analysis is presented, enabling a detailed understanding of strain-sensitive Raman data measured on Si nanobridges. Power-dependent measurements are required to account for the a priori unknown scattering efficiency related to size and geometry. The experimental data is used to assess the validity of previously published phonon deformation potentials.

Radiation Dose Effects in Trigate SOI MOS Transistors

Abstract: N-channel trigate SOI MOSFETs have been irradiated with 60 Co gamma rays at doses up to 6 Mrad(SiO2). The threshold voltage shift at 6 Mrad is less than 10 mV in transistors with a gate length of 0.3 mum. At 6 Mrad(SiO2), the current drive reduction in the same devices is 10% if VG=0 V during irradiation and 20% if VG=1 V during the irradiation. The generation of positive charges in the BOX increases the electron concentration at the bottom interface of the silicon fins. Inversion electrons at the bottom interface have a higher mobility than the electrons at the (110)-oriented fin sidewalls. As a result, an increase of transconductance with dose is observed at moderate doses [<1 Mrad(SiO2)]. At higher doses, the usual mobility degradation caused by interface trap generation is observed