Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs

Abstract: We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.

Capacitated qualification management in semiconductor manufacturing

Abstract: In semiconductor manufacturing, machines are usually qualified to process a limited number of recipes related to products It is possible to qualify recipes on machines to better balance the workload on machines in a given toolset However, all machines of a toolset do not have equal uptimes and may further suffer from scheduled and unscheduled downtimes This may heavily impact an efficient recipe-to-machine qualification configuration In this paper, we propose indicators for recipe-to-machine qualification management based on the overall toolset workload balance under capacity constraints The models, deployed in industry, demonstrate that the toolset capacity must be considered while managing qualifications Industrial experiments show how capacity consideration leads to an optimal qualification configuration and therefore capacity utilization

Apparatus for delivering precursor gases to an epitaxial growth substrate

Abstract: This invention provides gas injector apparatus that extends into a growth chamber in order to provide more accurate delivery of thermalized precursor gases. The improved injector can distribute heated precursor gases into a growth chamber in flows that spatially separated from each other up until they impinge of a growth substrate and that have volumes adequate for high volume manufacture. Importantly, the improved injector is sized and configured so that it can fit into existing commercial growth chamber without hindering the operation of mechanical and robot substrate handling equipment used with such chambers. This invention is useful for the high volume growth of numerous elemental and compound semiconductors, and particularly useful for the high volume growth of Group III-V compounds and GaN.

SMART-CUT(R) technology for SOI: A new high volume application for ion implantation

Abstract: A high volume technology for forming Silicon-on Insulator (SOI) named Smart-Cut(R) is described. Its key feature is a hydrogen implant which irreversibly weakens the structure of the silicon crystal close to the Rp of implantation. This acts as an atomic level scalpel to lift off a thin layer of silicon which is transferred to a second wafer. Since this technology relies only on standard semiconductor manufacturing equipment, capacity increases and silicon market developments-such as 300 mm SOI wafer requirements-can be implemented with ease.

Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

Abstract: In this paper we explore for the first time the impact of an Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50mV DIBL reduction by using 10nm BOX thickness for NMOS and PMOS devices at 33nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299µm2 SRAM cell while maintaining an SNM of 296mV @ Vdd 1.1V.