Showing papers by "Soitec published in 2012"

Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Abstract: In this letter, we report the performance of high-κ /metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage currents are demonstrated for ultrascaled gate lengths with a high on-off ratio (Ion/Ioff) >; 106. For the first time, an SS lower than 70 mV/dec is achieved at LG = 13 nm for n-type and p-type transistors, highlighting excellent electrostatic integrity of trigate junctionless NW MOSFETs.

Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

Abstract: Strain in Si nanostructures is used to achieve higher carrier mobility, making these devices candidates for the next generation of transistors. Minamisawa et al. fabricate silicon nanowires subject to elastic tensile strain up to 4.5%, exceeding the limit achievable with the use of SiGe virtual substrates.

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

Abstract: For the first time, we report high performance hybrid channel ETSOI CMOS by integrating strained SiGe-channel (cSiGe) PFET with Si-channel NFET at 22nm groundrules. We demonstrate a record high speed ring oscillator (fan-out = 3) with delay of 8.5 ps/stage and 11.2 ps/stage at V DD = 0.9V and V DD = 0.7V, respectively, outperforming state-of-the-art finFET results. A novel “STI-last” integration scheme is developed to improve cSiGe uniformity and enable ultra high performance PFET with narrow widths. Furthermore, cSiGe modulates device V t , thus providing an additional knob to enable multi-V t while maintaining undoped channels for all devices.

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Abstract: In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

A Self-Rectifying $\hbox{AlO}_{y}$ Bipolar RRAM With Sub-50- $\mu\hbox{A}$ Set/Reset Current for Cross-Bar Architecture

Abstract: In this letter, a bipolar resistive switching RAM based on Ni/AlOy/n+-Si which exhibits high potential to realize transistor-free operation for cross-bar array is successfully demonstrated. The proposed device shows well-behaved bipolar memory performance with self-rectifying behavior in low-resistance state (>; 700 at 0.2 V), a high on/off resistance ratio (>;103), a good retention characteristic (>; 104 s at 100 °C ), and a wide readout margin for cross-bar architecture (number of word line N >; 25 for worst case condition).

Method for curing defects in a semiconductor layer

Abstract: A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C.

$\Omega$ -Gated Silicon and Strained Silicon Nanowire Array Tunneling FETs

Abstract: This letter presents experimental results on tunneling field-effect transistors featuring arrays of Ω-gated uniaxially strained and unstrained silicon nanowires. The gate control of a SiO2/poly-Si gate stack is compared with a high-k/metal gate stack. Steep inverse subthreshold slopes down to 76 mV/dec and relatively high on-currents were achieved with the combination of high-k/metal gate and strained silicon nanowires. We observed negative differential conductance in the output characteristics, which we attribute to hot-carrier effects in the strong electric fields at the reverse-biased tunnel junction.

Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs

Abstract: In this letter, we present a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements. We show the technique of determining isothermal condition using only the self-heating (thermal) dominated range of the spectrum. We use a self-consistent self-heating extraction scheme using both the real and imaginary parts of drain port admittance parameters. Appropriate thermal network is investigated, and a large amount of temperature rise due to self-heating is confirmed for short channel silicon-on-insulator MOSFETs with ultrathin body and buried oxide.

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

Abstract: High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/µm and 1.25mA/µm, and I eff of 0.95mA/µm and 0.70mA/µm at I off =100nA/µm and V DD of 1V, for NFET and PFET, respectively.

Tunneling field-effect transistor with a strained Si channel and a Si0.5Ge0.5 source

Abstract: We report on n -channel tunneling field-effect transistors (TFET) with a tensile strained Si channel and a compressively strained Si 0.5 Ge 0.5 source. The device shows good performance with an average subthreshold swing S of 80 mV/dec over a drain current range of more than 3 orders of magnitude. We observed that the on-current increases exponentially with the back gate voltage. At a back gate voltage of 8 V, the on-current was enhanced by a factor of 1.6. The back gate also improves the on/off current ratio. Low temperature measurements show a slightly temperature dependent S , characteristic for a tunneling dominated device.

Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

Abstract: The impact of body-thickness scaling on strain-induced carrier-mobility enhancement in thin-body CMOSFETs with high-k/metal gate stacks, based on quantum-mechanical simulations calibrated with measured data, is presented to provide insight into device performance enhancement trends for future technology nodes.

Electromagnetic simulations of a photonic luminescent solar concentrator

Abstract: Luminescent solar concentrators (LSC) are used in photovoltaic applications to concentrate direct and diffuse sunlight without tracking. We employed 2D FDTD simulations to investigate the concept of a photonic LSC (PLSC), where the luminescent material is embedded in a photonic crystal to mitigate the primary losses in LSCs: the escape cone and reabsorption. We obtain suppressed emission inside the photonic band gap, which can be utilized to reduce reabsorption. Furthermore, the efficiency of light guiding is strongly enhanced in a broad spectral range, reaching up to 99.7%. Our optimization of design parameters suggests emitting layers of sub-wavelength thickness.

Semiconductor structures including fluidic microchannels for cooling and related methods

Abstract: Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.

High-Performance Germanium $\Omega$ -Gate MuGFET With Schottky-Barrier Nickel Germanide Source/Drain and Low-Temperature Disilane-Passivated Gate Stack

Abstract: We report high-performance p-channel Ω-gate germanium (Ge) p-channel multigate field-effect transistor (MuGFET) with low-temperature Si2H6 surface passivation and Schottky-barrier nickel germanide (NiGe) metallic source/drain, fabricated on high-quality germanium-on-insulator (GeOI) substrates using sub-400°C process modules. As compared with other reported p-channel multigate Ge devices formed by top-down approaches, the Ge MuGFETs in this letter have a record-high ON-state current ION of ~450 μA/μm at VGS - VTH = -1 V and VDS = - 1 V. High peak intrinsic saturation transconductance of ~740 μS/μm and low OFF-state current are reported. We also study the effect of fin or channel doping on Ge MuGFET performance. The simple MuGFET process developed using GeOI substrate would be a good reference for future 3-D Ge device fabrication.

20 nm Gate length Schottky MOSFETs with ultra-thin NiSi/epitaxial NiSi2 source/drain

Abstract: Schottky barrier (SB)-MOSFETs with NiSi and epitaxial NiSi2 S/D contacts with gate lengths as small as 20 nm are presented. Epitaxial NiSi2 FETs show higher on-currents than corresponding NiSi devices due to its lower SB height. A striking observation is that tunnelling currents through the fairly large SB decrease at very short gate lengths in SB-MOSFETs, in contrast to the scaling behavior of conventional MOSFETs. Simulations indicate that the potential in the channel increases due to overlap of the high source and drain barriers with decreasing gate length, leading to lower currents. Boron implantation into the silicide (IIS) was used to lower the SBH. Devices with epitaxial NiSi2 show an improved performance after barrier lowering by (IIS). It is shown, that the parasitic potential increase of the two S/D Schottky barriers can be either minimized by IIS and by enhanced gate control due to EOT scaling using high-k as the gate oxide.

A Self-Rectifying $\hbox{HfO}_{x}$ -Based Unipolar RRAM With NiSi Electrode

Abstract: In this letter, a unipolar resistive switching random access memory (RAM) based on NiSi/HfOx/TiN structure is demonstrated, which is compatible with NiSi S/D in advance CMOS technology process Highlights of the demonstrated resistive RAM include the following: 1) CMOS-technology-friendly materials and process; 2) excellent self-rectifying behavior in low-resistance state (>; 103 at 1 V); 3) well-behaved memory performance, such as high on/off resistance ratio (>; 102) and good retention characteristics (>;105 s at 125 °C ); and 4) wide readout margin for high-density cross-point memory devices (number of word lines 106 for the worst case condition)

Method of manufacturing a base substrate for a semi-conductor on insulator type substrate

Abstract: A method and system are provided for manufacturing a base substrate that is used in manufacturing semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.

Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

Abstract: A comprehensive study of the impact of back biasing on carrier transport behavior in Ultra-Thin Body and BOX (UTBB) Fully Depleted SOI (FD-SOI) MOSFETs and its implications for deeply scaled device performance is presented.

Parasitic bipolar impact in 32 nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology

Abstract: In this paper we explore the impact of the parasitic bipolar in undoped channel Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32 nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The static parasitic bipolar latch occurs at a drain bias superior to the circuit operation alimentation. The several type of ground plane and forward or reverse back biasing do not modify significantly the bipolar breakdown voltage. The thicker EOT gate oxide is more sensible to parasitic bipolar breakdown. Finally, results have been reinforced by using calibrated TCAD simulation tool.

Process for fabricating a silicon-on-insulator structure

Abstract: Embodiments of the invention relate to a process for fabricating a silicon-on-insulator structure comprising the following steps: providing a donor substrate and a support substrate, only one of the substrates being covered with an oxide layer; forming, in the donor substrate, a weak zone; plasma activating the oxide layer; bonding the donor substrate to the support substrate in a partial vacuum; implementing a bond-strengthening anneal at a temperature of 350° C. or less causing the donor substrate to cleave along the weak zone; and carrying out a heat treatment at a temperature above 900° C. A transition from the temperature of the bond-strengthening anneal to the temperature of the heat treatment may be achieved at a ramp rate above 10° C./s.

Hole Mobilities of $\hbox{Si/Si}_{0.5}\hbox{Ge}_{0.5}$ Quantum-Well Transistor on SOI and Strained SOI

Abstract: Hole mobilities of quantum-well p-MOSFETs on strained Si (sSi)/Si0.5Ge0.5/strained SOI (sSOI) and Si/Si0.5Ge0.5/SOI heterostructure substrates are investigated as a function of temperature. Ge interdiffusion during annealing in highly strained Si0.5Ge0.5 on SOI is reduced by the growth of Si0.5Ge0.5 layer on biaxially tensely strained SOI. As a result, the sSi/Si0.5Ge0.5/sSOI transistors showed significantly higher hole mobilities than the Si/Si0.5Ge0.5/SOI device at low temperatures.

Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length

Abstract: We fabricated highly stressed Fully Depleted Silicon-On-Insulator (FDSOI) n and pMOSFETs reaching I ON,n /I ON,p =1148/1014µA/µm drive current at I OFF,n /I OFF,p =55/16nA/µm leakage current (V DD =1V) with excellent V T -matching (A VT <1.5mV.µm). These short channel performances are well correlated and quantitatively explained by the effectiveness of strained SOI (sSOI), Contact-Etch-Stop-Layers (CESL) and SiGe raised sources and drains. sSOI improves I ON,n up to 22% and degrades SiGe sources and drains efficiency for pMOSFETs. However, 0° (<110>) orientation remains the best configuration for high-stress pMOSFETs and provides the best trade-off for CMOS.

Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices

Abstract: Methods of fabricating semiconductor devices that include interposers include the formation of conductive vias through a material layer on a recoverable substrate. A carrier substrate is bonded over the material layer, and the recoverable substrate is then separated from the material layer to recover the recoverable substrate. A detachable interface may be provided between the material layer and the recoverable substrate to facilitate the separation. Electrical contacts that communicate electrically with the conductive vias may be formed over the material layer on a side thereof opposite the carrier substrate. Semiconductor structures and devices are formed using such methods.

Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates

Abstract: For the first time, CMOS devices on UTBOX 25nm combined with strained SOI (sSOI) substrates have been demonstrated. A 20% Ion boost is highlighted with these substrates compared to the standard UTBB SOI ones. Performance up to 1530µA/µm @ Ioff=100nA/µm (Vd 1V) for a nominal Lg=30nm with a CET of 1.5nm for the NMOS has been achieved. The viability of this substrate has been demonstrated thanks to our hybrid process, through threshold voltage modulation and leakage current reduction, with back biasing for short devices. In addition, cell current improvement of 23% in 0.12µm2 bitcell is noticed for sSOI at the same stand-by current vs the standard UTBB SOI. Finally, the functionality of hybrid ESD device underneath the BOX is demonstrated.

Method for transferring a monocrystalline semiconductor layer onto a support substrate

Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.

Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped Nisi 2 tunnel junctions

Abstract: Planar and nanowire (NW) tunneling field effect transistors (TFETs) have been fabricated on ultra thin strained and unstrained SOI with shallow doped Nickel disilicide (NiSi 2 ) source and drain (S/D) contacts. We developed a novel, self-aligned process to form the p-i-n TFETs which greatly easies their fabrication by tilted dopant implantation using the high-k/metal gate as a shadow mask and dopant segregation. Two methods of dopant segregation are compared: Dopant segregation based on the “snow-plough” effect of dopants during silicidation and implantation into the silicide (IIS) followed by thermal outdiffusion. High drive currents of up to 60 μA/μm of planar p-TFETs were achieved indicating good silicide/silicon tunneling junctions. The non linear temperature dependence of the inverse subthreshold slope S indicates typical TFET behavior. Strained Si NW array n-TFETs with omega shaped HfO 2 /TiN gates showed high drive currents of 7 μA/μm @ 1V V dd and steep inverse subthreshold slopes with minimum values of 50mV/dec due to the smaller band gap of strained Si and optimized electrostatics.

Hole Transport in Strained $\hbox{Si}_{0.5} \hbox{Ge}_{0.5}$ QW-MOSFETs With $\langle\hbox{110}\rangle$ and $\langle\hbox{100}\rangle$ Channel Orientations

Abstract: Hole velocity and mobility are extracted from quantum-well (QW) biaxially strained Si0.5Ge0.5 channel metal-oxide-semiconductor field-effect transistors (MOSFETs) on silicon-on-insulator wafers. Devices have been fabricated at sub-100-nm gate length with HfO2/TiN gate stacks. A significant hole mobility enhancement over the strained Si mobility curve is observed for QW MOSFETs. We also discuss the relationship between velocity and mobility of the strained SiGe channels with high Ge content for 〈100〉 and 〈110〉 crystal directions. Whereas the mobility increases by 18% for 〈100〉 with respect to 〈110〉, it translates into a modest 8% velocity increase.

Delta-Doping of Epitaxial GaN Layers on Large Diameter Si(111) Substrates

Abstract: We report on silicon n-type delta (δ)-doping of gallium nitride (GaN) epitaxial layers grown by metalorganic chemical vapor deposition (MOCVD) on silicon (111) substrates. In a series of group III–nitride epitaxial structures a ~1-µm-thick Si bulk-doped GaN layer is replaced by 100, 50, 10, 5, or 1 Si δ-doped planes. While Si bulk-doping of GaN aggrandizes the in-plane tensile stress and the wafer bow with respect to undoped structures, δ-doping is found to reduce both stress and wafer bow. Two-dimensional carrier sheet densities between 1012 and 1013 cm-2 per δ-doped plane and electron mobilities of 1429 cm2 V-1 s-1 are achieved.

Differential sense amplifier without dedicated precharge transistors

Abstract: The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors.