Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Method for manufacturing a semiconductor on insulator structure having low electrical losses

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Formation and characterization of ultra-thin Ni silicides on strained and unstrained silicon

Abstract: Ultra thin Ni-silicides were formed on silicon-on-insulator (SOI) and biaxially tensile strained Si-on-insulator (SSOI) substrates. Epitaxial NiSi 2 layers were formed with a 3 nm Ni layer at T>400°C, while a polycrystalline NiSi layer was with a 5nm thick Ni layer. The NiSi 2 layer quality advances with increasing temperature. A very thin Pt interlayer, to incorporate Pt into NiSi, forming Ni 1-x Pt x Si, improves the thermal stability, the interface roughness and lowers the contact resistivity. The Schottky barrier heights (SBH) of these silicides were measured on n-Si(100). Ni 1-x Pt x Si shows the highest SBH. The SBH of NiSi 2 layers decreases by improving the layer interface. Surprisingly, the contact resistivity of epitaxial NiSi 2 is about one order of magnitude lower than that of NiSi on both, As and B doped SOI and SSOI, The lowest value of 7×10−8 Ω cm2 was measured on B doped SSOI.

Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H

Abstract: We have performed systematic measurements of the splitting kinetics induced by H-only and He+H sequential ion implantation into relaxed Si0.8Ge0.2 layers and compared them with the data obtained in Si. For H-only implants, Si splits faster than Si0.8Ge0.2. Sequential ion implantation leads to faster splitting kinetics than H-only in both materials and is faster in Si0.8Ge0.2 than in Si. We have performed secondary ion mass spectrometry, Rutherford backscattering spectroscopy in channeling mode, and transmission electron microscopy analyses to elucidate the physical mechanisms involved in these splitting phenomena. The data are discussed in the framework of a simple phenomenological model in which vacancies play an important role.

Process, stack and assembly for separating a structure from a substrate by electromagnetic radiation

Abstract: A method for separating a structure from a substrate through electromagnetic irradiations (EI) belonging to a spectral range comprises the steps of a) providing the substrate, b) forming an absorbent separation layer on the substrate, c) forming the structure to be separated on the separation layer, d) exposing the separation layer to the electromagnetic irradiations (EI) via the substrate such that the separation layer breaks down under the effect of the heat stemming from the absorption, the method being notable in that it comprises a step b1) of forming a transparent thermal barrier layer on the separation layer, the exposure period and the thickness of the thermal barrier layer being adapted such that the temperature of the structure to be separated remains below a threshold during the exposure period, beyond which threshold, faults are likely to appear in the structure.

300 mm InGaAsOI substrate fabrication using the Smart Cut TM technology

Abstract: In this work we demonstrate for the first time 300 mm InGaAs on Insulator (InGaAs-OI) substrates. A 30 nm thick InGaAs layer was successfully transferred using low temperature Direct Wafer Bonding (DWB) and the Smart CutTM technology. The epitaxial growing process has been optimized to reduce the surface roughness of the InGaAs film at around 1.5 nm RMS. HR-XRD characterization on the transferred InGaAs layer indicates that the layer remains crystalline.