Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Flexible RF/Microwave Switch-PIN Diodes Using Single-Crystal Si-Nanomembranes

Abstract: We report, to the best of our knowledge, the first realization of flexible single-crystal Si PIN diodes that are monolithically integrated on low-cost, low-temperature, flexible plastic substrate. 200-nm thin Si (001) nanomembrane is deprived from silicon-on-insulator (SOI) substrate after selective n-and p-type doping on the designated regions. The detailed fabrication of Si-nanomembrane (SiNM) PIN diodes on plastic substrate is described. The flexible SiNM PIN diodes demonstrate typical rectifying characteristics. S-parameter measurements on these PIN diodes show an insertion loss of less than 1.7 dB with isolation higher than 20 dB from DC up to 5 GHz at low bias conditions.

Structure of elastically strain-sharing silicon(110) nanomembranes

Abstract: Nanomembranes composed of single-crystal, tensilely strained Si(110) and compressively strained SiGe(110) layers have been fabricated from silicon-on-insulator (SOI) substrates. Elastic strain sharing is demonstrated for a trilayer structure consisting of a 12 nm Si/80 nm Si0.91Ge0.09 film epitaxially grown on a 12 nm thick (110) oriented Si template layer that is subsequently released from its handle substrate. X-ray diffraction on the as-grown and released structures confirms a virtually dislocation-free membrane with a tensile strain of 0.23±0.02% in the Si(110) layers after release. Lower growth temperatures in molecular beam epitaxy allow for smoother growth fronts than are possible using chemical vapour deposition.

Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic V th tuning and RF shielding applications

Abstract: 3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the $I_{ON}$ performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.

Process for fabricating a heterostructure limiting the formation of defects

Abstract: The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.

Gate-induced floating-body effect (GIFBE) in fully depleted triple-gate n-MOSFETs

Abstract: The gate-induced floating-body effect GIFBE) in triple-gate FETs is systematically investigated as a function of fin width and back-gate bias. GIFBE is due to body charging by the gate tunneling current and gives rise to a second peak in the transconductance. It occurs even in fully depleted (FD) devices, when the back-gate is driven from depletion to accumulation. It is found that the front-gate still maintains FD characteristics even though the GIFBE appears. GIFBE strongly decreases in narrow fins where the fringing field between the lateral gates prevents the back interface to reach accumulation. We show that GIFBE also depends on delay time and drain voltage.