Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

20 nm Gate length Schottky MOSFETs with ultra-thin NiSi/epitaxial NiSi2 source/drain

Abstract: Schottky barrier (SB)-MOSFETs with NiSi and epitaxial NiSi2 S/D contacts with gate lengths as small as 20 nm are presented. Epitaxial NiSi2 FETs show higher on-currents than corresponding NiSi devices due to its lower SB height. A striking observation is that tunnelling currents through the fairly large SB decrease at very short gate lengths in SB-MOSFETs, in contrast to the scaling behavior of conventional MOSFETs. Simulations indicate that the potential in the channel increases due to overlap of the high source and drain barriers with decreasing gate length, leading to lower currents. Boron implantation into the silicide (IIS) was used to lower the SBH. Devices with epitaxial NiSi2 show an improved performance after barrier lowering by (IIS). It is shown, that the parasitic potential increase of the two S/D Schottky barriers can be either minimized by IIS and by enhanced gate control due to EOT scaling using high-k as the gate oxide.

Method of collective manufacture of leds and structure for collective manufacture of leds.

Abstract: The invention relates to a method of collective manufacturing of light-emitting diode (LED) devices comprising formation of elemental structures (150) each comprising an n- type layer (132), an active layer (133) and a p-type layer (134), the method comprising: - reduction of the lateral dimensions of part of each elemental LED structure (150); - formation of a portion of insulating material (139) on the sides of the elemental structures (150); - formation of n-type electrical contact pads (145) and p-type electrical contact pads (138); - deposition of a conductive material layer (141) on the elemental structures (150) and polishing of the conductive material layer (141); and - bonding by molecular adhesion of a second substrate (50) on the polished surface (70a) of said structure (70).

Double-Gate MOSFETs: Is Gate Alignment Mandatory?

Abstract: Double-gate (DG) MOSFETs promise to enhance transistor capabilities beyond the limits of conventional CMOS technology. In this paper, we study for the first time the impact of gate misalignment in “non-ideal” DG devices that may be much easier to fabricate than self-aligned versions. Drain current, transconductance, series resistance effects, subthreshold slope and carrier concentration profiles are simulated for different architectures, based on a 50nm long SOI MOSFET. We compare single gate, ideal aligned DG, and non-aligned DG transistors in which unequal gate lengths are used to compensate for the gate misalignment. We find that non-aligned DG devices are competitive with and even, in some cases, superior to ideal DG MOS, albeit with unusual gm curves.

Multiple SOI layers by multiple Smart-Cut/sup (R)/ transfers

Abstract: Silicon on insulator (SOI) technologies are now entering mainstream applications, with recent announcements regarding for instance microprocessor applications. One condition for this to happen has been proof that SOI material manufacturing processes exist that are compatible with such industrial developments (availability, cost, quality, etc.). Among those processes, the Smart-Cut/sup (R)/ process is based on layer transfer from one substrate to another (Bruel, 1996). Stacking monocrystalline silicon on another silicon substrate with a silica layer in between is then possible and indeed is being used on a industrial scale to manufacture SOI wafers. Beyond simple SOI wafers that can also be high value added substrates for other applications such as photonics, sensors and other micromachining purposes, we demonstrate in this paper how the Smart-Cut/sup (R)/ process can be seen as a basic step and how this process can be used to realize multiple SOI wafers, allowing different crystalline and/or amorphous layers to be stacked.