Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Defect delineation and characterization in SiGe, Ge and other semiconductor-on-insulator structures

Abstract: The first part of this paper deals with the standard etching techniques (Secco, Schimmel, Wright etch…) used for defects delineation in Si, SiGe, Ge and in new engineered substrates made from these starting materials, such as Silicon-on-Insulator (SOI), strained and extra-strained Silicon-on-Insulator (sSOI and XsSOI) and Ge-on-Insulator (GeOI). We focus in the second part on the new, chromium-free etching techniques which have recently been developed: chemical solutions containing other oxidizing agents (such as organic peracids, additional compounds such as bromine, iodine etc.) and gaseous HCl etching. We compare the performances of standard etching solutions with those of chromium-free etching techniques and list the specificities of the different techniques. Finally, we attempt to link defect etching results with those coming from physical characterization techniques (such as Raman spectroscopy, X-ray diffraction and Pseudo-MOSFET mobility measurements). A few similar studies can be found in the literature. Extensive work is however still necessary to establish a proper correlation between selective etching and those techniques. Up to now, defect selective etching techniques are the most sensitive ones for an accurate evaluation of crystalline quality.

Metallic carrier for layer transfer and methods for forming the same

Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer.

Germanium Multiple-Gate Field-Effect Transistors Formed on Germanium-on-Insulator Substrate

Abstract: We demonstrate the integration of high performance p-channel Germanium Multiple-Gate Field-Effect Transistors (MuGFETs) on a Germanium-on-Insulator substrate. Detailed process conditions are documented in this paper. The effects of Ge fin doping concentration on the electrical performance of Ge MuGFETs are discussed, and this could be useful for further device optimization. It is found that a higher fin doping leads to better control of short-channel efforts of Ge MuGFETs but degrades the on-state current and transconductance. High on-state current for Ge MuGFETs is reported in this paper.

Analysis of the latch and breakdown phenomena in N and P channel thin film SOI MOSFET's as a function of temperature

Abstract: A study of the latch and breakdown phenomena in thin film N- and P-channel SOI MOSFET's is performed as a function of temperature. For P-type MOSFET's, for which no investigation of the parasitic bipolar transistor has been carried out, we show that latch problems are observed in the subhalf-micrometer range, while this feature is emphasized in the micrometer range for N-channel transistors. In addition, it is demonstrated by theoretical considerations and experimental results that these parasitic effects are strongly reduced at liquid nitrogen temperature and vanish almost entirely at liquid helium temperature. Similar improvements are obtained at low temperature in both N and P-channel SIMOX MOSFET's. >

Creation of an electrically conducting bonding between two semi-conductor elements

Abstract: A method of creating an electrically conducting bonding between a face of a first semiconductor element and a face of a second semiconductor element using heat treatment. The method applies the faces one against the other with the placing between them of at least one layer of a material configured to provide, after heat treatment, an electrically conducting bonding between the two faces. The deposited layers are chosen so that the heat treatment does not induce any reaction product between said material and the semi-conductor elements. Then, a heat treatment is carried out.