Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

MOSFETs with high mobility channel materials and higher-k/metal gate stack

Abstract: Integration of lanthanum lutetium oxide (LaLuO 3 ) with a к value of 30 is demonstrated on high mobility biaxially tensile strained Si (sSi) and compressively strained SiGe for fully depleted n/p-MOSFETs as a gate dielectric. N-MOSFETs on sSi fabricated with a full replacement gate process indicated very good electrical performance with steep subthreshold slopes of ∼72 mV/dec and I on /I off ratios up to 109. Strained SOI (sSOI) channel devices show higher electron mobility of 385 cm2/Vs compared to the reference device on SOI which has a mobility of 188 cm2/Vs. P-MOSFETs fabricated on sSi/Si 0.5 Ge 0.5 /sSOI heterostructure with a gate first process showed a subthreshold swing of 92 mV/dec and an I on /I off ratio of 105. The extracted hole mobilities are similar to the reference device with HfO 2 as gate dielectric, and are much higher than the hole mobilities in Si.

RF Small- and Large-Signal Characteristics of CPW and TFMS Lines on Trap-Rich HR-SOI Substrates

Abstract: The main objective of this paper is to evaluate RF losses and nonlinear behavior of coplanar wave- guide (CPW) and thin-film microstrip (TFMS) lines from room temperature up to 175 °C fabricated on two different types of high resistivity (HR) silicon-on-insulator (SOI) substrates. One standard high-resistivity and one trap-rich (TR) substrates, Soitec RFeSI90 product, are used. It is also shown that by using stacked CPW lines on the TR HR-SOI wafer, transmission lines with performances as high as TFMS lines are achievable, with low losses and low-harmonic distortion, while providing much more flexibility in their design. Through measurements, it is shown that the TR HR SOI substrate shows good stability in terms of losses and linearity up to 120 °C.

SiC Power Devices on QUASIC and SiCOI Smart-Cut® Substrates: First Demonstrations

Abstract: Wafer bonding technologies have been recognized to provide new substra tes uctures suitable for the development of Si power devices. Among the multipl e examples that could be listed, the possibility to generate PN junctions without thick epita xial growth and lateral devices onto dielectrically isolated substrates such as SOI (Silicon On Insulator) are significant examples of the interest proposed by wafer bonding. Thin film substrates obtai ned with the Smart-Cut® technology such as SiCOI (SiC On Insulator) substrates for la tera devices and QUASIC substrates for vertical power devices have already been demonstrated. In this ar icle, we review the recent developments in the field of SiC power devices using these two kinds of SiC Smart-Cut  substrates. Lateral and vertical Schottky diodes have been proces sed onto SiCOI and QUASIC substrates as a demonstration of feasibility. Simulations, results and prospects are presented in this article. Introduction Previous works have been focused on the demonstration and characteriza tion of SiCOI substrates (SiC On Insulator) [1] and QUASIC substrates [2]. In both cases, physical and electrical characterizations have proved that the crystallinity and main elec trical features of the SiC transferred layer are not altered by the Smart-Cut® process [ 1]. Moreover, CVD epitaxial SiC regrowth performed using bulk-like growth conditions is possible onto QUASIC substrates [2]. In this article, we will first focus on the fabrication and electr ical characteristics of vertical Schottky diodes onto vertically conductive and epitaxially SiC regrown on QUA SIC substrates. Secondly, electrical simulation, fabrication and electrical results of l ateral Schottky devices onto SICOI material will be presented and discussed. QUASIC Substrates for vertical power devices This substrate is designed to be compared with conventional 4H SiC b ulk substrates with low resistivity and low defect density. Some convincing technical demons trations have already been demonstrated onto QUASIC substrates. The possibility to grow a high qual ity epi ayer with good morphological and electrical properties is one main result. Secondly, the demonstration that the presence of the WSi2 bonding layer between the seed layer (trans fer ed using the Smart-Cut® process) and the SiC carrier substrate induces no electrical degradation on the current path is also one main point [2]. A Schottky diode structure has been fabricated on one QUASIC substr ate. The epitaxial stack has been grown in bulk-like conditions in a horizontal cold wall reactor at atmospheric pressure and at a temperature of 1450°C. The epitaxial sequence comprises an n+ buffer la yer directly grown on the Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 813-818 doi:10.4028/www.scientific.net/MSF.433-436.813 © 2003 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific.net. (Semanticscholar.org-12/03/20,10:57:03) transferred layer (1 μm thick, doping level 1e18 at/cm3), and an n t ype drift region with a doping level around 1e16 at/cm3. The thickness of the drift layer is about 6 μ m. The electrical resistivities of both the thin transferred layer and the SiC carrier substrate a e assumed to be 0.03 ohm.cm. Finally, the electrical resistivity of the buried WSi2 layer is assumed to be 50 μohm.cm. A simple Schottky device has been then manufactured. Vertical Schottky diodes wer then fabricated with titanium dots on top and titanium full sheet back side metallization followed by a 400 °C a nnealing. Figure 1 : cross section of Schottky diode fabricated onto epilaye r stack grown onto QUASIC substrate The device has no edge termination but it is important to notice tha t the structure involves the SiC epitaxial layers of a 600V Schottky diode. The complete stack is summarized i n figure 1. Room temperature I(V) forward and reverse measurements These measurements have been performed onto Schottky diodes of differe nt surface areas (0.05 mm and 2 mm). A four probes method has been used. I(V) characteristics are show n in figure 2. Small diodes (0.05 mm ) exhibit classical rectifier behavior (figure 2a) whereas some large diodes (2 mm2) exhibit an excess forward current (figure 2b), in the exponenti al regime (below 1 V), probably induced by a two barriers behavior. In correlation, we observe a larger reverse current for the large diodes. This effect has been already observed for Ti / 4H SiC diodes on commercial bulk SiC substrates [3]. Several measurements performed on diodes with the same diameter show that among diodes, the measured excess currents are not reproducible. Thus, the most probable reason for such an effect can be attributed to intrinsic material o r metal/SiC interfacial defects on the grown structure. This behavior was also observed onto commercial subst rates [3], but we cannot also exclude that this effect is not induced by the QUASIC substrate. Figure 2a) I(V) on a 0.05 mm 2 device 2b) I(V) on a 2 mm 2 device with a double Schottky barriers behavior 2 1 0 1 2 1 .10 12 1 .10 11 1 .10 10 1 .10 9 1 .10 8 1 .10 7 1 .10 6 1 .10 5 1 .10 4 1 .10 3 0.01 0.1 TENSION (V) C O U R A N T ( A )

Bonded semiconductor structures and methods of forming same

Abstract: Embodiments of the invention include methods and structures for fabricating a semiconductor structure, and, particularly for improving the planarity of a bonded semiconductor structure comprising a processed semiconductor structure and a semiconductor structure.