Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Systems for forming semiconductor materials by atomic layer deposition

Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.

Evaluation of sSOI wafers for 22nm node and beyond

Abstract: The transition to fully-depleted (FD) transistor technology is taking place today, either towards planar architectures on SOI wafers [1] or towards 3D-like architectures (FinFET or Trigate) [2]. The reason for this change is better electrostatic control, and reduction or even complete elimination of random dopant fluctuations, leading to much improved Vt variability.

Impact of effective capacitance area on the characterization of SOI Wafers by Split-C(V) in Pseudo-MOSFET configuration

Abstract: The Pseudo-MOSFET is a very successful characterization technique which can be further enriched by adopting split-C(V) measurements for mobility evaluation. In this work, we investigate the impact of the effective surface on the accurate evaluation of gate-to-channel capacitance in Pseudo-MOSFETs. The surprising dependence of the effective area on the AC signal frequency has been analyzed and modelled for a configuration with an arbitrary number of needles.

Smart Cut/spl trade/ transfer of 300 mm [110] and (100) Si layers for hybrid orientation technology

Abstract: In hybrid-orientation technology (HOT), devices are fabricated on hybrid substrate with [110] and (100) orientations to achieve significant PMOS performance enhancement Smart cut process is an important step in the substrate engineering for HOT We investigate the details of layer transfer in the substrates of different orientations and presents the characteristics of product [110] SOI wafers For the first time, we show that H platelet distributions, splitting kinetics and evolution of post-split surface morphology demonstrate strong substrate orientation dependence Certain modifications of critical process steps in generic smart cut process flow are required to fabricate high quality [110] SOI wafers

Strain engineering of ultra-thin silicon-on-insulator structures using through-buried-oxide ion implantation and crystallization

Abstract: We report a novel way of introducing strain in Ultra-Thin Body and Buried-Oxide (UTBB) SOI structures by Ge + implant into the underlying Si substrate and the formation of localized SiGe regions underneath the buried oxide (BOX) by Crystallization. The localized SiGe regions result in local deformation of the ultra-thin Si. Compressive strain of up to −0.55% and −1.2% were detected by Nano-Beam Diffraction (NBD) at the center and the edge, respectively, of a 50 nm wide ultra-thin Si region located between two local SiGe regions. The under-the-BOX SiGe regions may be useful for strain engineering of ultra-thin body transistors formed on UTBB-SOI substrates.