Soitec

About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).

Current status and future perspectives of wafer bonding (Smart Cut/spl trade/) SOI technology

Abstract: Current status and future perspectives for SOI (silicon-on-insulator) using Smart Cut technology will be reviewed. First, industrial growth of SOI production mainly driven by MRJ and low-power LSI applications will be presented, with a focus on the rapid growth of 300mm SOI wafer production and advancement of Si thickness control. Next, versatility of the bonding (Smart Cut) technology will be described, exemplified by the future device candidates, such as strained-Si on insulator, ultrathin FD structures, FinFET, combination of different crystal orientations, and Ge-on-insulator. Thirdly, it will be shown that bonding technology can be extended to realize totally different functions, such as SO (silicon-on-quartz) and combination of Si technology with compound semiconductors, which cannot be realized by conventional bulk Si nor bulk compound semiconductors. Throughout this presentation, it will be shown that wafer bonding technology provides not only solutions for survival of CMOS scaling, but also contributes to diversification of functionality in LSIs, which will meet the needs of the future IT society.

Correlation between cathodoluminescent and electrical properties of dislocation network in the space charge region of Schottky‐diode

Abstract: A detailed investigation and comparison of low-temperature cathodoluminescent (CL) and electrical properties of DN is presented. The correlations between the CL, electron beam induced current (EBIC), and CV measurements using the DC electric bias as a parameter are established and analyzed in the scope of the calculated theoretical model. A new CL measurement technique that is complimentary to conventional space charge region spectroscopy (SCRS) methods such as DLTS and MCTS is proposed and the first experimental results using this new approach are described. Shallow dislocation-related level Ev+Et=0.1 eV is shown to be responsible for D1 dislocation-related luminescence line. (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Back gate in select transistor for eDRAM

Abstract: The present invention relates to an eDRAM memory element comprising a first storage node (1120, 1220), a bitline node (1040) for accessing the value stored in the storage node, and a select transistor (1130, 1230), controlling access from the bitline node to the storage node, wherein the select transistor has a front gate (1132, 1232) and a back gate (4510, 4511).

Improving the quality of a thin layer through high-temperature thermal annealing

Abstract: The invention relates to a method for forming a structure comprising a layer in a semiconductor material taken from a donor substrate, the method comprising the following successive steps, (a) implantation of atomic species to form a zone of embrittlement in the donor substrate at a given depth; (b) assembly of the donor substrate to a receiver substrate; (c) supply of energy to detach the layer taken from.the donor substrate at the embrittlement zone by implementing detachment annealing carried out at high temperature; (d) finishing treatment of the layer taken in view of improving its surface condition, characterized in that in detachment step (c), the high-temperature detachment annealing develops according to an upgrade allowing a high temperature to be reached, said high temperature corresponding to the maximum temperature of the detachment annealing and in that the duration of exposure to said high temperature is limited in such a way as to prevent the appearance of significant defectivity at the surface of the structure obtained after detachment.

Method for transferring a layer of a semiconductor and substrate comprising a confinement structure

Abstract: A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that are distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into a donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer.