Institution
Soitec
Company•Bernin, France•
About: Soitec is a company organization based out in Bernin, France. It is known for research contribution in the topics: Layer (electronics) & Silicon on insulator. The organization has 589 authors who have published 1062 publications receiving 13737 citations. The organization is also known as: Soitec (France).
Papers published on a yearly basis
Papers
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01 Sep 2019TL;DR: To improve SOI layer thickness variability, a 2nd generation chemical thinning process step is proposed and improvements are demonstrated on 100% and on 75% of the wafer surface, respectively.
Abstract: Beyond 65FD-SOI, 28FD-SOI, 22FD-SOI production granted technologies, continuous SmartCutTM development support advanced SOI requirements. To improve SOI layer thickness variability, a 2nd generation chemical thinning process step is proposed. 11% and 25% improvements are demonstrated on 100% and on 75% of the wafer surface, respectively. This improved product is ready for pre-production.
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19 Sep 2019TL;DR: In this paper, a relaxation substrate comprising a support and a flow layer on the support that includes first and second groups of blocks having different viscosities at a relaxation temperature is provided.
Abstract: A method for manufacturing a plurality of crystalline semiconductor islands having different lattice parameters includes providing a relaxation substrate comprising a support and a flow layer on the support that includes first and second groups of blocks having different viscosities at a relaxation temperature. The relaxation substrate also comprises a plurality of strained crystalline semiconductor islands on the flow layer, the islands of a first group being located on the first group of blocks and islands of a second group being located on the second group of blocks. The relaxation substrate is then heat treated at a relaxation temperature higher than or equal to the glass transition temperature of at least one block of the flow layer to cause differentiated lateral expansion of the first and second groups of islands such that the first and second groups of relaxed islands then have different lattice parameters.
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30 Mar 2020TL;DR: In this paper, a method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support.
Abstract: A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.
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TL;DR: In this paper, high resistivity gold-implanted silicon substrates developed for radio frequency (RF) applications were characterized by varying PICTS (Photo-Induced Current Transient Spectroscopy) measurement conditions such as the illumination wavelength, and the authors identified the signature and the nature of four dominant traps.
Abstract: In this study, high-resistivity gold-implanted silicon substrates developed for radio frequency (RF) applications were characterized. By varying PICTS (Photo-Induced Current Transient Spectroscopy) measurement conditions such as the illumination wavelength, we identified the signature and the nature of four dominant traps. Two were electron traps and the others were hole traps. All of the related defects involved gold atoms. RF simulations of coplanar waveguide transmission lines integrated on these substrates were carried out, based on the trap properties extracted from PICTS results. A good agreement between RF experimental data and simulations was achieved by tuning the trap concentrations. Finally, the gold density extracted from the fit was successfully compared with the secondary ion mass spectrometry profile and an explanation of the role of the traps in RF behavior of the substrate was given.
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22 Nov 2013TL;DR: In this paper, the hourly AC power output of a passively-cooled Concentrator Photovoltaic (CPV) system in terms of 6 easily-determined system parameters and 4 measured or computed environmental variables is analyzed.
Abstract: A formula is proposed that characterizes the hourly AC power output of a passively-cooled Concentrator Photovoltaic (CPV) system in terms of 6 easily-determined system parameters and 4 measured or computed environmental variables. The model was tested on a grid-connected Soitec CPV system at Sede Boqer in the Negev Desert of Israel and found to be accurate to within typically ± 5% for any given hour of the year.
Authors
Showing all 590 results
Name | H-index | Papers | Citations |
---|---|---|---|
Michael R. Krames | 65 | 321 | 18448 |
Bich-Yen Nguyen | 47 | 273 | 6557 |
Iuliana Radu | 37 | 237 | 5026 |
George K. Celler | 36 | 233 | 5964 |
Andreas Gombert | 31 | 176 | 3597 |
Fabrice Letertre | 29 | 180 | 2707 |
Bruno Ghyselen | 28 | 175 | 2943 |
Kiyoshi Mitani | 26 | 122 | 1966 |
Bernard Aspar | 25 | 99 | 1910 |
Mariam Sadaka | 25 | 98 | 1780 |
Stefan Degroote | 24 | 93 | 2335 |
Konstantin Bourdelle | 24 | 132 | 2236 |
Joff Derluyn | 23 | 75 | 1877 |
Carlos Mazure | 20 | 151 | 1552 |
Philippe Flatresse | 20 | 73 | 1175 |