Showing papers on "Silicon on insulator published in 2020"

Enhanced Kerr Nonlinearity and Nonlinear Figure of Merit in Silicon Nanowires Integrated with 2D Graphene Oxide Films.

Abstract: Layered two-dimensional (2D) graphene oxide (GO) films are integrated with silicon-on-insulator (SOI) nanowire waveguides to experimentally demonstrate an enhanced Kerr nonlinearity, observed throu

Compact Graphene Plasmonic Slot Photodetector on Silicon-on-Insulator with High Responsivity

Abstract: Graphene has extraordinary electro-optic properties and is therefore a promising candidate for monolithic photonic devices such as photodetectors. However, the integration of this atom-thin layer m...

Polarization-sensitive terahertz resonator using asymmetrical F-shaped metamaterial

Abstract: A design of tunable terahertz (THz) resonator by using asymmetrical F-shaped metamaterial (AFSM) is presented, which is composed of Au layer fabricated on silicon-on-insulator (SOI) substrate. There are three designs of AFSM with different length of F-shaped microstructure, which are 60 μm, 65 μm, and 70 μm kept other parameters as constant. The electromagnetic response of tunable THz resonator exhibits the switch function for single-band resonance at transverse magnetic (TM) mode and dual-band resonance at transverse electric (TE) mode by changing the gap between AFSM microstructures. These characterizations of device can be used for a THz filter at TM mode and a THz switch at TE mode. To compare the proposed AFSM device with and without a gap, that can be switched in the range of 0.20–0.40 THz for single-band switching resonance at TM mode and dual-band switching resonance at TE mode, respectively. These resonances are ultra-narrow bandwidths with a highest Q-factor of 40 at TE mode and kept as stable at 20 at TM mode. Such results are very suitable to be used for an environmental sensor. To further enhance the flexibility of AFSM device, it is exposed on ambient environment with different refraction index for high-efficiency environmental sensor with a correlation coefficient of 0.9999. This study paves a way to the possibility of high-sensitivity of tunable THz metamaterial in filter, switch, polarizer, and other applications.

Micro-Transfer-Printed III-V-on-Silicon C-Band Semiconductor Optical Amplifiers

Abstract: The micro-transfer-printing of prefabricated C-band semiconductor optical amplifiers (SOAs) on a silicon waveguide circuit is reported. The SOAs are 1.35 mm in length and 40 mu m in width. Dense arrays of III-V SOAs are fabricated on the source InP wafer. These can then be micro-transfer-printed on the target SOI photonic circuits in a massively parallel fashion. Additionally, this approach allows for greater flexibility in terms of integrating different epitaxial layer structures on the same SOI waveguide circuit. The technique allows integrating SOAs on a complex silicon photonic circuit platform without changing the foundry process-flow. Two different SOA designs with different optical confinement factor in the quantum wells of the III-V waveguide are discussed. This allows tuning the small-signal gain and output saturation power of the SOA. The design with higher optical confinement in the quantum wells has a small-signal gain of up to 23 dB and an on-chip saturation power of 9.2 mW at 140 mA bias current and the lower optical confinement factor design has a small-signal gain of 17 dB and power saturation of 15 mW at 160 mA of bias current.

Waveguide-integrated high-performance magneto-optical isolators and circulators on silicon nitride platforms

Abstract: Optical isolators and circulators are important components for photonic integrated circuits. Despite significant progress on silicon-on-insulator (SOI) platforms, integrated optical isolators and circulators have rarely been reported on silicon nitride (SiN) platforms. In this paper, we report monolithic integration of magneto-optical (MO) isolators on SiN platforms with record-high performances based on standard silicon photonics foundry process and MO thin film deposition. We successfully grow high-quality MO garnet thin films on SiN with large Faraday rotation up to -−5900deg/cm. We show superior MO figure of merit (FoM) of MO/SiN waveguides compared to that of MO/SOI in an optimized device design. We demonstrate transverse magnetic (TM)/transverse electric (TE) mode broadband and narrowband optical isolators and circulators on SiN with high isolation ratio, low cross talk, and low insertion loss. In particular, we observe 1 dB insertion loss and 28 dB isolation ratio in a SiN racetrack resonator-based isolator at 1570.3 nm wavelength. The low thermo-optic coefficient of SiN also ensures excellent temperature stability of the device. Our work paves the way for integration of high-performance nonreciprocal photonic devices on SiN platforms.

Bufferless 15 µm III-V lasers grown on Si-photonics 220 nm silicon-on-insulator platforms

Abstract: Efficient III-V lasers directly grown on Si remain the “holy grail” for present Si-photonics research. In particular, a bufferless III-V laser grown on the Si-photonics 220 nm silicon-on-insulator (SOI) platform could seamlessly bridge the active III-V light sources with the passive Si-based photonic devices. Here we report on the direct growth of bufferless 1.5 µm III-V lasers on industry-standard 220 nm SOI platforms using metal organic chemical vapor deposition (MOCVD). Taking advantage of the constituent diffusivity at elevated growth temperatures, we first devised a MOCVD growth scheme for the direct hetero-epitaxy of high-quality III-V alloys on the 220 nm SOI wafers through synergizing the conventional aspect ratio trapping (ART) and the lateral ART methods. In contrast to prevalent epitaxy inside V-grooved pockets, our method features epitaxy inside trapezoidal troughs and thus enables the flexible integration of different III-V compounds on SOIs with different Si device layer thicknesses. Then, using InP as an example, we detailed the growth process and performed extensive study of the crystalline quality of the epitaxial III-V. Finally, we designed and fabricated both pure InP and InP/InGaAs lasers, and we achieved room-temperature lasing in both the 900 nm band and the 1500 nm band under pulsed optical excitation. Direct epitaxy of these in-plane and bufferless 1.5 µm III-V lasers on the 220 nm SOI platform suggests the imminent interfacing with Si-based photonic devices and the subsequent realization of fully integrated Si-based photonic circuits.

Surface acoustic wave photonic devices in silicon on insulator

Abstract: Opto-mechanical interactions in planar photonic integrated circuits draw great interest in basic research and applications. However, opto-mechanics is practically absent in the most technologically significant photonics platform: silicon on insulator. Previous demonstrations required the under-etching and suspension of silicon structures. Here we present surface acoustic wave-photonic devices in silicon on insulator, up to 8 GHz frequency. Surface waves are launched through absorption of modulated pump light in metallic gratings and thermoelastic expansion. The surface waves are detected through photo-elastic modulation of an optical probe in standard race-track resonators. Devices do not involve piezo-electric actuation, suspension of waveguides or hybrid material integration. Wavelength conversion of incident microwave signals and acoustic true time delays up to 40 ns are demonstrated on-chip. Lastly, discrete-time microwave-photonic filters with up to six taps and 20 MHz wide passbands are realized using acoustic delays. The concept is suitable for integrated microwave-photonics signal processing

Heterogeneously Integrated ITO Plasmonic Mach-Zehnder Interferometric Modulator on SOI

Abstract: Densely integrated active photonics is key for next generation on-chip networks for addressing both footprint and energy budget concerns. However, the weak light-matter interaction in traditional active Silicon optoelectronics mandates rather sizable device lengths. The ideal active material choice should avail high index modulation while being easily integrated into Silicon photonics platforms. Indium tin oxide (ITO) offers such functionalities and has shown promising modulation capacity recently. Interestingly, the nanometer-thin unity-strong index modulation of ITO synergistically combines the high group-index in hybrid plasmonic with nanoscale optical modes. Following this design paradigm, here, we demonstrate a spectrally broadband, GHz-fast Mach-Zehnder interferometric modulator, exhibiting a high efficiency signified by a miniscule VpL of 95 Vum, deploying an one-micrometer compact electrostatically tunable plasmonic phase-shifter, based on heterogeneously integrated ITO thin films into silicon photonics. Furthermore we show, that this device paradigm enables spectrally broadband operation across the entire telecommunication near infrared C-band. Such sub-wavelength short efficient and fast modulators monolithically integrated into Silicon platform open up new possibilities for high-density photonic circuitry, which is critical for high interconnect density of photonic neural networks or applications in GHz-fast optical phased-arrays, for example.

Nonduplicate Polarization-Diversity 32 × 32 Silicon Photonics Switch Based on a SiN/Si Double-Layer Platform

Abstract: We fabricate and characterize a polarization-diversity 32 × 32 silicon photonics switch by newly introducing SiN overpass waveguides onto our nonduplicate polarization-diversity path-independent insertion-loss switch. The SiN overpass waveguides are used to simplify the optical paths with a uniform path length between the edge couplers and the switch matrix and significantly reduce the number of waveguide intersections. The switch chip is fabricated using a 300-mm silicon-on-insulator wafer pilot line. The fabricated switch comprises more than 7,600 components, making this the largest ever complementary-metal-oxide-semiconductor-based silicon photonics circuit. The switch chip is electrically and optically packaged and evaluated for a sampled port connection with 32 paths, with an average on-chip loss of ∼35 dB and an average polarization-dependent loss of 3.2 dB where 75% of the measured paths exhibit a loss of less than 3 dB. The differential group delay is measured to be 1.7 ps. The performance can be further improved by optimizing the device design.

Engineering telecom single-photon emitters in silicon for scalable quantum photonics

Abstract: We create and isolate single-photon emitters with a high brightness approaching $10^5$ counts per second in commercial silicon-on-insulator (SOI) wafers. The emission occurs in the infrared spectral range with a spectrally narrow zero phonon line in the telecom O-band and shows a high photostability even after days of continuous operation. The origin of the emitters is attributed to one of the carbon-related color centers in silicon, the so-called G center, allowing purification with the $^{12}$C and $^{28}$Si isotopes. Furthermore, we envision a concept of a highly-coherent scalable quantum photonic platform, where single-photon sources, waveguides and detectors are integrated on a SOI chip. Our results provide a route towards the implementation of quantum processors, repeaters and sensors compatible with the present-day silicon technology.

Performance evaluation of linearity and intermodulation distortion of nanoscale GaN-SOI FinFET for RFIC design

Abstract: This work presents, performance evaluation of linearity and intermodulation distortion of novel nanoscale Gallium Nitride (GaN) Silicon-on-Insulator (SOI) N-channel FinFET (n-FinFET) for RFIC design and results so obtained are simultaneously compared with conventional (Si-based) FinFET and bulk GaN-based FinFET with 8 nm gate length. It is found that the proposed device enhances on-current (ION) by four times and thereby transconductance, subthreshold slope, threshold voltage, surface potential, and energy band (conduction band energy and valence band energy) profiles have been improved at ultra-low voltage power supply (VDS = 0.1 V). Thus, the improved electrical performance of GaN-SOI FinFET makes it suitable for low power and high-performance CMOS circuits. Also a further investigative study has been performed on the linearity behavior of GaN-SOI FinFET and the outcomes of the study have been compared with the results of the GaN Bulk FinFET and the conventional Silicon FinFET. The SOI device shows better linear performance in the likes of higher-order voltage and current intercept points as VIP2, VIP3, IIP3, and 1-dB compression point with lesser harmonic distortions as HD2, HD3 and, IMD3. Thus, the results with higher efficiency, better linearity, and distortionless performance pave the way for RFIC design.

Low Loss, Large Bandwidth Fiber-Chip Edge Couplers Based on Silicon-on-Insulator Platform

Abstract: Fiber-chip edge couplers are extensively used in integrated silicon photonic for the coupling of light between optical fibers and planar silicon waveguide circuits. Here, we experimentally demonstrate three kinds of edge couplers with eased fabrication process, two fork shape, and one dual-trident SWG shape, based on Silicon-on-Insulator platform. A commercial lensed fiber with mode field diameter of 6 μm is used. The coupling performance and fabrication tolerance are theoretically analyzed and verified by 3D-FDTD simulation. The experimental results show that these edge couplers pose low coupling losses and large bandwidths simultaneously. At the wavelength of 1.55 μm, the coupling losses are 1.25 dB/facet, 1.49 dB/facet, 1.82 dB/facet for fork1, fork2, and dual-trident SWG couplers, respectively. The measured wavelength bandwidths in which the loss below 2 dB are 114 nm, 102 nm, 92 nm, respectively.

An Electret-Augmented Low-Voltage MEMS Electrostatic Out-of-Plane Actuator for Acoustic Transducer Applications.

Abstract: Despite the development of energy-efficient devices in various applications, microelectromechanical system (MEMS) electrostatic actuators yet require high voltages to generate large displacements. In this respect, electrets exhibiting quasi-permanent electrical charges allow large fixed voltages to be integrated directly within electrode structures to reduce or eliminate the need of DC bias electronics. For verification, a − 40 V biased electret layer was fabricated at the inner surface of a silicon on insulator (SOI) structure facing a 2 μm gap owing to the high compatibility of silicon micromachining and the potassium-ion-electret fabrication method. A − 10 V electret-augmented actuator with an out-of-plane motion membrane reached a sound pressure level (SPL) of 50 dB maximum with AC input voltage of V i n = 5 V pp alone, indicating a potential for acoustic transducer usage such as microspeakers. Such devices with electret biasing require only the input signal voltage, thus contributing to reducing the overall power consumption of the device system.

Ultra-Efficient Silicon-on-Insulator Grating Couplers With Backside Metal Mirrors

Abstract: Coupling of light from off-chip into highly complex silicon-based devices is currently focus of efforts and research. In this work, the experimental demonstration of a −0.50 dB (89%) coupling efficiency in the C-band with the help of an aperiodic grating coupler design in a 250 nm silicon-on-insulator (SOI) technology is shown. Further, this work reports about the latest results regarding focusing grating couplers with footprints of only 30 μ m × 30 μm and a measured coupling efficiency of up to −0.93 dB (81%) at 1549 nm. Efficient grating coupler arrays are realized by using an expanded backside metal mirror-strip for the application of fiber arrays. In addition, this work presents aperiodic silicon grating couplers with an enhanced bandwidth to overcome the limited usability of grating couplers in wavelength division multiplexing (WDM) systems.

Comprehensive Study on Chip-Integrated Germanium Pin Photodetectors for Energy-Efficient Silicon Interconnects

Abstract: Optical interconnects are promising alternatives to copper-based wirings in on-chip communications. Recent advances in integrated group-IV nanophotonics should address a range of challenges related with speed, energy consumption, and cost. Monolithically integrated germanium pin photodetectors on silicon-on-insulator (SOI) waveguides are indispensable devices in this buoyant research field. Here, we comprehensively investigate the opto-electrical properties of hetero-structured pin photodetectors. All photodetectors were fabricated on top of 200-mm SOI substrates using industrial-scale semiconductor manufacturing processes. Under a low-bias voltage supply of 1 V, pin photodetectors exhibit dark-currents from 5 nA to 100 nA, dark current densities from 0.404 A/cm 2 to 0.808 A/cm 2 , responsivities in a range of 0.17 A/W to 1.16 A/W, and cut-off frequencies from 7 GHz to 35 GHz, respectively. Such achievements make them promising for use in power-efficient optical links operating at 40 Gbps, with a device energy dissipation of only few fJ per bit.

Optimized Substrate for Improved Performance of Stacked Nanosheet Field-Effect Transistor

Abstract: The recently proposed stacked nanosheet-field-effect transistor (SNSH-FET) is considered as a promising candidate for continued scaling with silicon. While using punchthrough-stopper-doped (or) ground-plane-doped silicon substrate (PTS-Si substrate) in which the top part of the substrate is doped heavily with the p-type (for nMOS) impurity to avoid punchthrough leakage between the source and the drain. The heavily doped p–n junction formed at the drain–substrate junction acts as a reverse-biased tunnel diode during ${V}_{{\text {DS}}}$ biasing, which leads to large substrate leakage current. We presented SuperSteep-Retrograde silicon substrate (SSR-Si substrate) configuration which reduces the tunneling current by increasing the tunnel barrier width and diminishing the peak electric field at the drain–substrate junction. The SSR-Si substrate is achieved by growing a lightly doped or undoped layer of silicon (SSR-buffer layer) on the PTS-doped substrate. The impact of SSR-buffer layer thickness is studied and the optimal thickness (12 nm) is presented. The vertically stacked channels’ configuration leads to position-dependent current densities in different channels due to position-dependent series resistance. Herein, we present nanosheet width optimization as a solution to achieve homogeneous current ratio between all the channels thereby resulting in better linearity performance. The self-heating and RF performance of the presented SSR-Si substrate is compared with the silicon-on-insulator (SOI) substrate. The results show that SSR-Si substrate can be a better substrate for SNSH-FET because of better self-heating performance.

Ultra-thin silicon-on-insulator waveguide bend based on truncated Eaton lens implemented by varying the guiding layer thickness

Abstract: Silicon-on-insulator (SOI) waveguides with different geometries have been employed to design various integrated optical components. Reducing the bending radius of the SOI waveguides with low bending loss is essential in minimizing the footprint of light-wave circuits. The propagating mode is less confined in the core of the ultra-thin SOI waveguide and penetrates to substrate and cladding, leading to higher bending loss compared to conventional SOI waveguides with a thicker guiding layer. Although various bending mechanisms have been utilized to reduce the bending loss of conventional SOI waveguides, the ultra-thin SOI waveguide bends have not been studied in detail. In this paper, we present a 60-nm-thick SOI waveguide bend based on the truncated Eaton lens implemented by varying thickness of the guiding layer. The three-dimensional full-wave simulations reveal that the designed waveguide bend, with a radius of 3.9 μm, reduces the bending loss from 3.3 to 0.42 dB at the wavelength of 1550 nm. Moreover, the bending loss for the wavelength range of 1260–1675 nm is lower than 0.67 dB while the bending loss in the C-band is lower than 0.45 dB.

InAs/GaAs quantum dot narrow ridge lasers epitaxially grown on SOI substrates for silicon photonic integration.

Abstract: Monolithic integration of III-V laser sources on standard silicon-on-insulator (SOI) substrate has been recognized as an enabling technology for realizing Si-based photonic integration circuits (PICs). The Si-based ridge lasers employing III-V quantum dot (QD) materials are gaining significant momentum as it allows massive-scalable, streamlined fabrication of Si photonic integrated chips to be made cost effectively. Here, we present the successful fabrication of InAs/GaAs QD ridge lasers monolithically grown on {111}-faceted SOI hollow substrates. The as-cleaved Fabry-Perot (FP) narrow ridge laser is achieved with a relatively low threshold current of 50 mA at room temperature under pulse current operation. The maximum working temperature achieved is up to 80 oC. The promising lasing characteristics of such SOI-based InAs/GaAs QD ridge lasers with low threshold current and small footprint provide a viable route towards large-scale, low-cost integration of laser sources on SOI platform for silicon photonic integration purpose.

Silicon photonics for telecom and data-com applications

Abstract: In recent decades, silicon photonics has attracted much attention in telecom and data-com areas. Constituted of high refractive-index contrast waveguides on silicon-on-insulator (SOI), a variety of integrated photonic passive and active devices have been implemented supported by excellent optical properties of silicon in the mid-infrared spectrum. The main advantage of the silicon photonics is the ability to use complementary metal oxide semiconductor (CMOS) pro-cess-compatible fabrication technologies, resulting in high-volume production at low cost. On the other hand, explosively growing traffic in the telecom, data center and high-performance computer demands the data flow to have high speed, wide bandwidth, low cost, and high energy-efficiency, as well as the photonics and electronics to be integrated for ultra-fast data transfer in networks. In practical applications, silicon photonics started with optical interconnect transceivers in the data-com first, and has been now extended to innovative applications such as multi-port optical switches in the telecom network node and integrated optical phased arrays (OPAs) in light detection and ranging (LiDAR). This paper overviews the progresses of silicon photonics from four points reflecting the recent advances mentioned above. CMOS-based silicon photonic platform technologies, applications to optical transceiver in the data-com network, applications to multi-port optical switches in the telecom network and applications to OPA in LiDAR system.

Vernier effect-based tunable mid-infrared sensor using silicon-on-insulator cascaded rings.

Abstract: Vernier effect has been captivated as a promising approach to achieve high-performance photonic sensors. However, experimental demonstration of such sensors in mid-infrared (MIR) range, which covers abundant absorption fingerprints of molecules, is still lacking. Here, we report Vernier effect-based thermally tunable photonic sensors using cascaded ring resonators fabricated on the silicon-on-insulator (SOI) platform. The radii and the coupling gaps in two rings are investigated as key design parameters. By applying organic liquids on our device, we observe an envelope shift of 48 nm with a sensitivity of 3000 nm/RIU and an intensity drop of 6.7 dB. Besides, our device can be thermally tuned with a sensitivity of 0.091 nm/mW. Leveraging the characteristic molecular absorption in the MIR, our work offers new possibilities for complex index sensing, which has wide applications in on-chip photonic sensors.

Source-Drain Junction Engineering Schottky Barrier MOSFETs and their Mixed Mode Application

Abstract: In this paper, a new structure for a silicon on insulator Schottky barrier MOSFET (SOI SB-MOSFET) has been proposed. The simulated device is calibrated with experimental result. Here n + pocket doping segregation in the source and drain side have been used. The simulated electrical characteristics of the proposed device With Source Extension (WSE) and With Source Drain Extension (WSDE) reveal more remarkable reduction in drain induced barrier tunneling (DIBT), high Ion/Ioff and low Subthreshold swing(SS) than conventional device. Furthermore, the effect of varying temperature has been investigated on subthreshold swing for various oxide thickness (Tox) and silicon film thickness (TSi). Moreover, proposed SB-MOSFETs have been used in the inverter circuit, exhibit a high gain (˷12) and Noise Margin (NMH = 0.4 and NML = 0.46).

A Single-Electron Injection Device for CMOS Charge Qubits Implemented in 22-nm FD-SOI

Abstract: This letter presents a single-electron injection device for position-based charge qubit structures implemented in 22-nm fully depleted silicon-on-insulator CMOS. Quantum dots are implemented in local well areas separated by tunnel barriers controlled by gate terminals overlapping with a thin 5-nm undoped silicon film. Interface of the quantum structure with classical electronic circuitry is provided with single-electron transistors that feature doped wells on the classic side. A small $0.7\times 0.4\,\,\mu \text{m}^{2}$ elementary quantum core is co-located with control circuitry inside the quantum operation cell which is operating at 3.5 K and a 2-GHz clock frequency. With this apparatus, we demonstrate a single-electron injection into a quantum dot.

Phosphorus-free 1.5 µm InAs quantum-dot microdisk lasers on metamorphic InGaAs/SOI platform.

Abstract: III–V semiconductor lasers epitaxially grown on silicon, especially on a silicon-on-insulator (SOI) platform, have been considered one of the most promising approaches to realize an integrated light source for silicon photonics. Although notable achievements have been reported on InP-based 1.5 µm III–V semiconductor lasers directly grown on silicon substrates, phosphorus-free 1.5 µm InAs quantum dot (QD) lasers on both silicon and SOI platforms are still uncharted territory. In this work, we demonstrate, to the best of our knowledge, the first phosphorus-free InAs QD microdisk laser epitaxially grown on SOI substrate emitting at the telecommunications S-band by growing metamorphic InAs/InGaAs QDs on (111)-faceted SOI hollow structures. The lasing threshold power for a seven-layer InAs QD microdisk laser with a diameter of 4 µm is measured as 234 μW at 200 K. For comparison, identical microdisk lasers grown on GaAs substrate are also characterized. The results obtained pave the way for an on-chip 1.5 µm light source for long-haul telecommunications.

Optimization of photoluminescence from W centers in a silicon-on-insulator

Abstract: W centers are trigonal defects generated by self-ion implantation in silicon that exhibit photoluminescence at 1.218 µm. We have shown previously that they can be used in waveguide-integrated all-silicon light-emitting diodes (LEDs). Here we optimize the implant energy, fluence and anneal conditions to maximize the photoluminescence intensity for W centers implanted in silicon-on-insulator, a substrate suitable for waveguide-integrated devices. After optimization, we observe near two orders of magnitude improvement in photoluminescence intensity relative to the conditions with the stopping range of the implanted ions at the center of the silicon device layer. The previously demonstrated waveguide-integrated LED used implant conditions with the stopping range at the center of this layer. We further show that such light sources can be manufactured at the 300-mm scale by demonstrating photoluminescence of similar intensity from 300 mm silicon-on-insulator wafers. The luminescence uniformity across the entire wafer is within the measurement error.

A 38 dB Gain, Low-Loss, Flat Array Antenna for 320–400 GHz Enabled by Silicon-on-Insulator Micromachining

Abstract: Two high-gain flat array antenna designs operating in the 320–400 GHz frequency range are reported in this article. The two antennas show the measured gains of 32.8 and 38 dBi and consist of a $16\times16$ (256) element array and a $32\times32$ (1024) element array, respectively, which are fed by a corporate H-tree beamforming network. The measured operation bandwidth for both antennas is 80 GHz [22% fractional bandwidth (FBW)], and the total measured efficiency is above −2.5 dB and above −3.5 dB for the two designs in the whole bandwidth. The low measured loss and large bandwidth are enabled by optimizing the designs to the process requirements of the silicon on insulator (SOI) micromachining technology used in this article. The total height of the antennas is 1.1 mm ( $1.2~\lambda $ at the center frequency), with sizes of 15 mm $\times $ 18 mm and 27 mm $\times $ 30 mm for both arrays. The antennas are designed to be directly mounted onto a standard WM-570 waveguide flange. The design, fabrication, and measurements of eight prototypes are discussed in this article and the performance of the antennas compared to the simulated data, as well as manufacturability and fabrication repeatability are reported in detail.

Highly sensitive silicon photonic temperature sensor based on liquid crystal filled slot waveguide directional coupler.

Abstract: A highly sensitive silicon photonic temperature sensor based on silicon-on-insulator (SOI) platform has been proposed and demonstrated. A two-mode nano-slot waveguide device structure cladded with a nematic liquid crystal (LC), E7, was adopted to facilitate strong light-matter interaction and achieve high sensitivity. The fabricated sensor was characterized by measuring the optical transmission spectra at different ambient temperatures. The extracted temperature sensitivities of the E7-filled device are 0.810 nm/°C around room temperature and 1.619 nm/°C near 50°C, which match well with simulation results based on a theoretical analysis. The results obtained represent the highest experimentally demonstrated temperature sensitivity for a silicon-waveguide temperature sensor on SOI platform. The slot waveguide directional coupler device configuration provides submicron one-dimensional spatial resolution and flexible selection in LC materials for designing temperature sensitivity and operational temperature range required by specific applications.

Hybrid III-V Silicon Photonic Crystal Cavity Emitting at Telecom Wavelengths.

Abstract: Photonic crystal (PhC) cavities are promising candidates for Si photonics integrated circuits due to their ultrahigh quality (Q)-factors and small mode volumes. Here, we demonstrate a novel concept of a one-dimensional hybrid III-V/Si PhC cavity which exploits a combination of standard silicon-on-insulator technology and active III-V materials. Using template-assisted selective epitaxy, the central part of a Si PhC lattice is locally replaced with III-V gain material. The III-V material is placed to overlap with the maximum of the cavity mode field profile, while keeping the major part of the PhC in Si. The selective epitaxy process enables growth parallel to the substrate, and hence in-plane integration with Si, and in-situ in-plane homo- and heterojunctions. The fabricated hybrid III-V/Si PhCs show emission over the entire telecommunication band from 1.2 to 1.6 μm at room temperature validating the device concept and its potential towards fully integrated light sources on silicon.

Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies

Abstract: This paper presents design considerations and methodology for D-band transformer-based Class-AB gain-boosting power amplifiers (PAs) in three advanced silicon technologies: 28 nm bulk CMOS (complementary metal oxide semiconductor), 22 nm FD-SOI (fully-depleted silicon on insulator), and 130 nm SiGe BiCMOS (Silicon-germanium bipolar-CMOS). Firstly, the choice of processes and models together with de-embedding approaches are discussed and described. Then, a general design flow for a transformer-based matching network (TMN) is introduced to accelerate the design of multistage PAs. Further, two gain-boosting topologies are analyzed. The influence of capacitive gain-boosting on PA performance (maximum available power gain G max , saturation power P sat , drain efficiency DE and power-added efficiency PAE) is studied for different silicon technologies after properly sizing the PA transistors to reach an optimum load resistance R opt . The inductive gain-boosting PA is explored and compared with the capacitive gain-boosting one in SiGe BiCMOS to achieve an even higher P sat while maintaining a high G max . Finally, A D-band 4-stage capacitive gain-boosting PA is fabricated in a 28 nm bulk CMOS process as a reference to verify the design methodology and simulation results, and its detailed design considerations are described. This prototyped D-band PA achieved the state-of-the-art results: a 22.5 dB G p, 6.6 % PAE, 8 dBm P sat and 81.1 FoM with only 0.0265 mm 2 core area.

Ultrasensitive and fast photoresponse in graphene/silicon-on-insulator hybrid structure by manipulating the photogating effect

Abstract: The hybrid structures of graphene with semiconductor materials based on photogating effect have attracted extensive interest in recent years due to the ultrahigh responsivity. However, the responsivity (or gain) was increased at the expense of response time. In this paper, we devise a mechanism which can obtain an enhanced responsivity and fast response time simultaneously by manipulating the photogating effect (MPE). This concept is demonstrated by using a graphene/silicon-on-insulator (GSOI) hybrid structure. An ultrahigh responsivity of more than 10(7) A/W and a fast response time of 90 Its were obtained. The specific detectivity D* was measured to be 1.46 X 10(13) Jones at a wavelength of 532 nm. The Silvaco TCAD modeling was carried out to explain the manipulation effect, which was further verified by the GSOI devices with different doping levels of graphene in the experiment. The proposed mechanism provides excellent guidance for modulating carrier distribution and transport, representing a new route to improve the performance of graphene/semiconductor hybrid photodetectors.