Showing papers on "Transistor published in 2003"

Thin-Film Transistor Fabricated in Single-Crystalline Transparent Oxide Semiconductor

Abstract: We report the fabrication of transparent field-effect transistors using a single-crystalline thin-film transparent oxide semiconductor, InGaO 3 (ZnO) 5 , as an electron channel and amorphous hafnium oxide as a gate insulator. The device exhibits an on-to-off current ratio of ∼10 6 and a field-effect mobility of ∼80 square centimeters per volt per second at room temperature, with operation insensitive to visible light irradiation. The result provides a step toward the realization of transparent electronics for next-generation optoelectronics.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

High Performance Silicon Nanowire Field Effect Transistors

Abstract: Silicon nanowires can be prepared with single-crystal structures, diameters as small as several nanometers and controllable hole and electron doping, and thus represent powerful building blocks for nanoelectronics devices such as field effect transistors. To explore the potential limits of silicon nanowire transistors, we have examined the influence of source-drain contact thermal annealing and surface passivation on key transistor properties. Thermal annealing and passivation of oxide defects using chemical modification were found to increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V‚s with peak values of 2000 nS and 1350 cm 2 /V‚s, respectively. The comparison of these results and other key parameters with state-of-the-art planar silicon devices shows substantial advantages for silicon nanowires. The uses of nanowires as building blocks for future nanoelectronics are discussed.

A low-power low-noise CMOS amplifier for neural recording applications

Abstract: There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.

Transistor structures and methods for making the same

Abstract: Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, Sn02, or In203. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO, Sn02or In2O3, the substantially insulating ZnO, Sn02, or In203 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

Transparent ZnO thin-film transistor fabricated by rf magnetron sputtering

Abstract: We fabricated ZnO thin-film transistors by rf magnetron sputtering on Si substrates held near room temperature. The best devices had field-effect mobility of more than 2 cm2/V s and an on/off ratio>106. These ZnO films had resistivity ∼105 ohm cm, with high optical transparency (>80% for wavelength >400 nm), and compressive stress <0.5 GPa. The combination of transparency in the visible, excellent transistor characteristics, and low-temperature processing makes ZnO thin-film transistors attractive for flexible electronics on temperature sensitive substrates.

Field-effect transistor on SrTiO3 with sputtered Al2O3 gate insulator

Abstract: A field-effect transistor has been constructed that employs a perovskite-type SrTiO3 single crystal as the semiconducting channel. This device functions as an n-type accumulation-mode device. The device was fabricated at room temperature by sputter-deposition of amorphous Al2O3 films as a gate insulator on the SrTiO3 substrate. The field-effect (FE) mobility is 0.1 cm2/V s and on-off ratio exceeds 100 at room temperature. The temperature dependence of the FE mobility down to 2 K shows a thermal-activation-type behavior with an activation energy of 0.6 eV.

Random networks of carbon nanotubes as an electronic material

Abstract: We report on the transport properties of random networks of single-wall carbon nanotubes fabricated into thin-film transistors. At low nanotube densities (∼1 μm−2) the networks are electrically continuous and behave like a p-type semiconductor with a field-effect mobility of ∼10 cm2/V s and a transistor on-to-off ratio ∼105. At higher densities (∼10 μm−2) the field-effect mobility can exceed 100 cm2/V s; however, in this case the network behaves like a narrow band gap semiconductor with a high off-state current. The fact that useful device properties are achieved without precision assembly of the nanotubes suggests the random carbon nanotube networks may be a viable material for thin-film transistor applications.

Solution-processed ambipolar organic field-effect transistors and inverters.

Abstract: There is ample evidence that organic field-effect transistors have reached a stage where they can be industrialized, analogous to standard metal oxide semiconductor (MOS) transistors. Monocrystalline silicon technology is largely based on complementary MOS (CMOS) structures that use both n-type and p-type transistor channels. This complementary technology has enabled the construction of digital circuits, which operate with a high robustness, low power dissipation and a good noise margin. For the design of efficient organic integrated circuits, there is an urgent need for complementary technology, where both n-type and p-type transistor operation is realized in a single layer, while maintaining the attractiveness of easy solution processing. We demonstrate, by using solution-processed field-effect transistors, that hole transport and electron transport are both generic properties of organic semiconductors. This ambipolar transport is observed in polymers based on interpenetrating networks as well as in narrow bandgap organic semiconductors. We combine the organic ambipolar transistors into functional CMOS-like inverters.

Active pixel sensor with intra-pixel charge transfer

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

TILOS: A posynomial programming approach to transistor sizing

Abstract: A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented. Let A be the sum of transistor sizes, T the longest delay through the circuit, and K a positive constant. Using a distributed RC model, each of the following three programs is shown to be convex: 1) Minimize A subject to T < K. 2) Minimize T subject to A < K. 3) Minimize AT K . The convex equations describing T are a particular class of functions called posynomials. Convex programs have many pleasant properties, and chief among these is the fact that any point found to be locally optimal is certain to be globally optimal TILOS (Timed Logic Synthesizer) is a program that sizes transistors in CMOS circuits. Preliminary results of TILOS’s transistor sizing algorithm are presented.

Close look at charge carrier injection in polymer field-effect transistors

Abstract: Parasitic contact resistance effects are becoming a major issue in organic transistors in that they can severely limit or even dominate their overall transistor performance. We present a systematic study of the contact resistance in bottom-contact polymer field-effect transistors made from poly(3-hexylthiophene) (P3HT) as well as poly-9,9′dioctyl-fluorene-co-bithiophene (F8T2). A microscopic approach based on noncontact scanning-probe potentiometry was used to directly separate the transport properties of the transistor channel and the electrode/polymer contacts, giving very accurate experimental access to both the source and drain contact resistance. The influence of the relevant parameters (temperature, electrode work function, ionization potential of the polymer, charge carrier mobility) on the source/drain contact resistance is investigated. We find that for “good” source/drain contacts that give rise to relatively small overall contact resistances (⩽50 kΩ cm), e.g., P3HT with chromium–gold electrodes...

High performance fully-depleted tri-gate CMOS transistors

Abstract: Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.

Single-electron transistors in heterostructure nanowires.

Abstract: Semiconductor-based single-electron transistors have been fabricated using heterostructure nanowire growth, by introducing a double barrier of InP into InAs nanowires. From electrical measurements, we observe a charging energy of 4 meV for the approximately 55 nm diameter and 100 nm long InAs islands between the InP barriers. The Coulomb blockade can be periodically lifted as a function of gate voltage for all devices, which is a typical signature of single-island transistors. Homogeneous InAs nanowires show no such effect for the corresponding voltage ranges.

High breakdown voltage AlGaN-GaN power-HEMT design and high current density switching behavior

Abstract: AlGaN-GaN power high-electron mobility transistors (HEMTs) with 600-V breakdown voltage are fabricated and demonstrated as switching power devices for motor drive and power supply applications. The fabricated power HEMT realized the high breakdown voltage by optimized field plate technique and the low on-state resistance of 3.3 m/spl Omega/cm/sup 2/, which is 20 times lower than that or silicon MOSFETs, thanks to the high critical field of GaN material and the high mobility in 2DEG channel. The fabricated devices also demonstrated the high current density switching of 850 A/cm/sup 2/ turn-off. These results show that AlGaN-GaN power-HEMTs are one of the most promising candidates for future switching power device for power electronics applications.

Semiconductor transistor having a stressed channel

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Flexible Nanotube Electronics

Abstract: Nanotube network transistors have been transferred to polymer supports. The polymer-supported networks can be bent through at least 60° angles without changing their electronic properties. They ope...

High-Performance Nanowire Electronics and Photonics on Glass and Plastic Substrates

Abstract: The merger of nanoscale building blocks with flexible and/or low cost substrates could enable the development of high-performance electronic and photonic devices with the potential to impact a broad spectrum of applications. Here we demonstrate that high-quality, single-crystal nanowires can be assembled onto inexpensive glass and flexible plastic substrates to create basic transistor and light-emitting diode devices. In our approach, the high-temperature synthesis of single-crystal nanowires is separated from ambient-temperature solution-based assembly to enable the fabrication of single-crystal-like devices on virtually any substrate. Silicon nanowire field-effect transistors were assembled on glass and plastic substrates and display device parameters rivaling those of single-crystal silicon and exceeding those of state-of-the-art amorphous silicon and organic transistors currently used for flexible electronics on plastic substrates. Nanowire transistor devices have been configured as low-threshold logi...

All-optical transistor action with bistable switching in a photonic crystal cross-waveguide geometry

Abstract: We demonstrate all-optical switching action in a nonlinear photonic crystal cross-waveguide geometry with instantaneous Kerr nonlinearity, in which the transmission of a signal can be reversibly switched on and off by a control input. Our geometry accomplishes both spatial and spectral separation between the signal and the control in the nonlinear regime. The device occupies a small footprint of a few micrometers squared and requires only a few milliwatts of power at a 10-Gbit/s switching rate by use of Kerr nonlinearity in AlGaAs below half the electronic bandgap. We also show that the switching dynamics, as revealed by both coupled-mode theory and finite-difference time domain simulations, exhibits collective behavior that can be exploited to generate high-contrast logic levels and all-optical memory.

Pentacene organic transistors and ring oscillators on glass and on flexible polymeric substrates

Abstract: We have fabricated organic thin film transistors, inverters, and ring oscillators on glass and on flexible polyethylene naphthalate, using the small-molecule hydrocarbon pentacene as the semiconductor and solution-processed polyvinylphenol as the gate dielectric. Depending on the choice of substrate, the transistors have a carrier mobility between 0.3 and 0.7 cm2/V s, an on/off current ratio between 105 and 106, and a subthreshold swing between 0.9 and 1.6 V/decade. To account for the positive switch-on voltage of the transistors, circuits were designed to operate with integrated level shifting. Depending on the type of substrate, ring oscillators have a signal propagation delay as low as 15 μs per stage.

Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

Abstract: In order to manage the active power consumption of high-performance digital designs, active leakage control techniques are required to provide significant leakage power savings coupled with fast time constants for entering and exiting idle mode. In this paper, dynamic sleep transistors and body bias are used in conjunction with clock gating to control active leakage for a 32-bit integer execution core in 130-nm CMOS technology. Measurements on pMOS sleep transistor reveal that lowest-leakage state is reached in less than 1 /spl mu/s, resulting in 37/spl times/ reduction in leakage power, while reactivation of block is achieved in less than two clock cycles. PMOS body bias reduces leakage power by 2/spl times/ with no performance penalty, and similar reactivation time. Power measurements at 4 GHz, 1.3 V, 75/spl deg/C demonstrate 8% total power reduction using dynamic body bias and 15% power reduction using a pMOS sleep transistor, for a typical activity profile.

Electroluminescent display devices

Abstract: An active matrix display device comprises an array of display pixels provided over a common substrate. Each pixel has a voltage-programmed current source circuit, a drive transistor and a light sensitive device for sensing the display element light output. The light sensitive device provides a current dependent on the display element output, and the light sensitive device and the current source circuit define a feedback control loop which controls the voltage provided to the gate of the drive transistor. This pixel circuit uses a current source circuit to provide a gate voltage to a drive transistor. This enables the current source circuit to operate at low current levels, and therefore under low voltage stress.

Contact resistance in organic transistors that use source and drain electrodes formed by soft contact lamination

Abstract: Soft contact lamination of source/drain electrodes supported by gold-coated high-resolution rubber stamps against organic semiconductor films can yield high-performance organic transistors. This article presents a detailed study of the electrical properties of these devices, with an emphasis on the nature of the laminated contacts with the p- and n-type semiconductors pentacene and copper hexadecafluorophthalocyanine, respectively. The analysis uses models developed for characterizing amorphous silicon transistors. The results demonstrate that the parasitic resistances related to the laminated contacts and their coupling to the transistor channel are considerably lower than those associated with conventional contacts formed by evaporation of gold electrodes directly on top of the organic semiconductors. These and other attractive features of transistors built by soft contact lamination suggest that they may be important for basic and applied studies in plastic electronics and nanoelectronic systems based ...

Nonlinear photonic crystal microdevices for optical integration.

Abstract: A four-port nonlinear photonic crystal system is discussed that exhibits optical bistability with negligible backscattering to the inputs, making it particularly suitable for integration with other active devices on the same chip. Devices based on this system can be made to be small Oλ3 in volume, have a nearly instantaneous response, and consume only a few milliwatts of power. Among many possible applications, we focus on an all-optical transistor and integrated optical isolation.

Semiconductor memory device

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can be operated with low power source voltage such that write-in speed is not reduced and of which power consumption is low. SOLUTION: At the time of read-out of data, a pseudo ground line VGj provided corresponding to a pair of bit lines BLj, /BLj of memory cells 11 i , j to be read out is connected to ground voltage GND through a transistor 31 j . Thereby, the bit line BLj (or /BLj) corresponding to a 'L' level is connected to ground voltage GND through an acceleration circuit AC in the memory cells 11 i , j , read-out speed is accelerated. At the time of write-in time of data, a pseudo ground line VGj provided corresponding to the pair of bit lines BLj, /BLj to be written is connected to power source voltage VDD through a transistor 33 j . Thereby, a current from the bit line BLj (or /BLj) of a 'H' level to the pseudo ground line VGj is prevented, and write-in speed is not reduced. COPYRIGHT: (C)2004,JPO

Power efficient charge pump in deep submicron standard CMOS technology

Abstract: A power-efficient charge pump is proposed. The use of low-voltage transistors and of a simple two-phase clocking scheme permits the use of higher operating frequencies compared to conventional solutions, thus obtaining high current, high efficiency, and small area. Measurements show good results for frequencies around 100 MHz. Two test patterns have been fabricated, one with three stages and one with five stages, in a 1.8-V 0.18-/spl mu/m triple-well standard CMOS digital process (six metals). High-voltage capacitors have been implemented using metal to metal parasitic capacitance.

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

Abstract: Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30 nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single-gate or double-gate devices, but that the corner plays a fundamental role in determining the device I-V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the subthreshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.

Source side self boosting technique for non-volatile memory

Abstract: A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

Method to fabricate dual metal CMOS devices

Abstract: The present invention relates generally to barrier layers in transistor gate stacks in integrated circuits, and to processes for forming such gate stacks.

Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit

Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.