Showing papers on "Transistor published in 2010"

100-GHz Transistors from Wafer-Scale Epitaxial Graphene

Abstract: The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon transistors of the same gate length.

Nanowire transistors without junctions

Abstract: All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

High-speed graphene transistors with a self-aligned nanowire gate

Abstract: Graphene has attracted considerable interest as a potential new electronic material. With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics. However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance. Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co(2)Si-Al(2)O(3) core-shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the self-alignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA μm(-1)) and transconductance (1.27 mS μm(-1)) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of f(T) = 100-300 GHz, with the extrinsic f(T) (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic f(T) of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths.

Reinventing germanium avalanche photodetector for nanophotonic on-chip optical interconnects

Abstract: A key element in the integration of microprocessor chips with optical communications circuits is a photodetector to mediate the optical and electronic signals. Germanium photodetectors are very attractive in this regard because they are compatible with conventional silicon circuitry, but they suffer from noise that limits their performance. Assefa et al. now show how the poor intrinsic noise characteristics of germanium can be overcome through the careful engineering of optical and electrical fields at the nanometre scale. The result is a compact and efficient photodetector that could enable a range of optoelectronic applications. To integrate microchips with optical communications a photodetector is required to mediate the optical and electronic signals. Although germanium photodetectors are compatible with silicon their performance is impaired by poor intrinsic noise. Here the noise is reduced by nanometre engineering of optical and electrical fields to produce a compact and efficient photodetector. Integration of optical communication circuits directly into high-performance microprocessor chips can enable extremely powerful computer systems1. A germanium photodetector that can be monolithically integrated with silicon transistor technology2,3,4,5,6,7,8 is viewed as a key element in connecting chip components with infrared optical signals. Such a device should have the capability to detect very-low-power optical signals at very high speed. Although germanium avalanche photodetectors9,10 (APD) using charge amplification close to avalanche breakdown can achieve high gain and thus detect low-power optical signals, they are universally considered to suffer from an intolerably high amplification noise characteristic of germanium11. High gain with low excess noise has been demonstrated using a germanium layer only for detection of light signals, with amplification taking place in a separate silicon layer12. However, the relatively thick semiconductor layers that are required in such structures limit APD speeds to about 10 GHz, and require excessively high bias voltages of around 25 V (ref. 12). Here we show how nanophotonic and nanoelectronic engineering aimed at shaping optical and electrical fields on the nanometre scale within a germanium amplification layer can overcome the otherwise intrinsically poor noise characteristics, achieving a dramatic reduction of amplification noise by over 70 per cent. By generating strongly non-uniform electric fields, the region of impact ionization in germanium is reduced to just 30 nm, allowing the device to benefit from the noise reduction effects13,14,15 that arise at these small distances. Furthermore, the smallness of the APDs means that a bias voltage of only 1.5 V is required to achieve an avalanche gain of over 10 dB with operational speeds exceeding 30 GHz. Monolithic integration of such a device into computer chips might enable applications beyond computer optical interconnects1—in telecommunications16, secure quantum key distribution17, and subthreshold ultralow-power transistors18.

Performance estimation of junctionless multigate transistors

Abstract: This paper describes the simulation of the electrical characteristics of a new transistor concept called the ‘‘Junctionless Multigate Field-Effect Transistor (MuGFET)”. The proposed device has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversion-mode devices with PN junctions at the source and drain. The simulation results indicate that the junctionless MuGFET is a very promising candidate for future decananometer MOSFET applications.

Are optical transistors the logical next step

Abstract: A transistor that operates with photons rather than electrons is often heralded as the next step in information processing, but optical technology must first prove itself to be a viable solution in many different respects.

GaN Power Transistors on Si Substrates for Switching Applications

Abstract: In this paper, GaN power transistors on Si substrates for power switching application are reported. GaN heterojunction field-effect transistor (HFET) structure on Si is an important configuration in order to realize a low loss and high power devices as well as one of the cost-effective solutions. Current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate. Furthermore, attempts for normally off GaN-FETs were examined. A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance (Ron) and a high breakdown voltage (Vb).

GaN Power Transistors on Si Substrates for Switching Applications Hybrid MOS-FET transistor devices with low on-resistance, high hold-voltages and high breakdown voltage promise to provide high-power, low-loss operation for switching applications.

Abstract: In this paper, GaN power transistors on Si substrates for power switching application are reported. GaN heterojunction field-effect transistor (HFET) structure on Si is an important configuration in order to realize a low loss and high power devices as well as one of the cost-effective solutions. Current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate. Furthermore, attempts for normally off GaN-FETs were exam- ined. A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance ðRonÞ and a high breakdown voltage ðVbÞ.

High-performance flexible graphene field effect transistors with ion gel gate dielectrics.

Abstract: A high-performance low-voltage graphene field-effect transistor (FET) array was fabricated on a flexible polymer substrate using solution-processable, high-capacitance ion gel gate dielectrics. The high capacitance of the ion gel, which originated from the formation of an electric double layer under the application of a gate voltage, yielded a high on-current and low voltage operation below 3 V. The graphene FETs fabricated on the plastic substrates showed a hole and electron mobility of 203 ± 57 and 91 ± 50 cm2/(V·s), respectively, at a drain bias of −1 V. Moreover, ion gel gated graphene FETs on the plastic substrates exhibited remarkably good mechanical flexibility. This method represents a significant step in the application of graphene to flexible and stretchable electronics.

Biocompatible and Biodegradable Materials for Organic Field-Effect Transistors

Abstract: Biocompatible-ingestible electronic circuits and capsules for medical diagnosis and monitoring are currently based on traditional silicon technology Organic electronics has huge potential for developing biodegradable, biocompatible, bioresorbable, or even metabolizable products An ideal pathway for such electronic devices involves fabrication with materials from nature, or materials found in common commodity products Transistors with an operational voltage as low as 4–5 V, a source drain current of up to 05 μ A and an on-off ratio of 3–5 orders of magnitude have been fabricated with such materials This work comprises steps towards environmentally safe devices in lowcost, large volume, disposable or throwaway electronic applications, such as in food packaging, plastic bags, and disposable dishware In addition, there is signifi cant potential to use such electronic items in biomedical implants

Length scaling of carbon nanotube transistors

Abstract: Carbon nanotube field-effect transistors are strong candidates in replacing or supplementing silicon technology. Although theoretical studies have projected that nanotube transistors will perform well at nanoscale device dimensions, most experimental studies have been carried out on devices that are about ten times larger than current silicon transistors. Here, we show that nanotube transistors maintain their performance as their channel length is scaled from 3 µm to 15 nm, with an absence of so-called short-channel effects. The 15-nm device has the shortest channel length and highest room-temperature conductance (0.7G₀) and transconductance (40 µS) of any nanotube transistor reported to date. We also show the first experimental evidence that nanotube device performance depends significantly on contact length, in contrast to some previous reports. Data for both channel and contact length scaling were gathered by constructing multiple devices on a single carbon nanotube. Finally, we demonstrate the performance of a nanotube transistor with channel and contact lengths of 20 nm, an on-current of 10 µA, an on/off current ratio of 1 x 10⁵, and peak transconductance of 20 µS. These results provide an experimental forecast for carbon nanotube device performance at dimensions suitable for future transistor technology nodes.

Flexible organic transistor memory devices.

Abstract: The flexible nonvolatile organic memory devices were developed on the plastic substrates based on the organic thin-film transistors embedding self-assembled gold nanoparticles (Au(NP)). The organic memory devices exhibited good programmable memory characteristics with respect to the program/erase operations, resulting in controllable and reliable threshold voltage shifts. Additionally, the endurance, data retention, and bending cyclic measurements confirmed that the flexible memory devices exhibited good electrical reliability as well as mechanical stability. The memory devices were composed of the solution-processed organic dielectric layers/metallic nanoparticles and the low-temperature processed organic transistors. Therefore, this approach could potentially be applied to advanced flexible/plastic electronic devices as well as integrated organic device circuits.

Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

Abstract: A tunneling field-effect transistor (TFET) is considered one of the most promising alternatives to a metal-oxide-semiconductor field-effect transistor due to its immunity to short-channel effects. However, TFETs have suffered from low on-current, severe ambipolar behavior, and gradual transition between on- and off -states. To address those issues, the authors have proposed hetero-gate-dielectric TFETs. The proposed device enhances on-current, suppresses ambipolar behavior, and makes abrupt on-off transition by replacing the source-side gate insulator with a high-k material, which induces a local minimum of the conduction band edge at the tunneling junction.

An Organic Nanoparticle Transistor Behaving as a Biological Spiking Synapse

Abstract: Molecule-based devices are envisioned to complement silicon devices by providing new functions or by implementing existing functions at a simpler process level and lower cost, by virtue of their self-organization capabilities. Moreover, they are not bound to von Neuman architecture and this feature may open the way to other architectural paradigms. Neuromorphic electronics is one of them. Here, a device made of molecules and nanoparticles-a nanoparticle organic memory field-effect transistor (NOMFET)—that exhibits the main behavior of a biological spiking synapse is demonstrated. Facilitating and depressing synaptic behaviors can be reproduced by the NOMFET and can be programmed. The synaptic plasticity for real-time computing is evidenced and described by a simple model. These results open the way to rate-coding utilization of the NOMFET in dynamical neuromorphic computing circuits.

Semiconductor storage device

Abstract: A semiconductor storage device is provided with a memory array including a plurality of memory cells. The plurality of memory cells includes: first and third memory cells arranged along one of an even-numbered row and an odd-numbered row, and a second memory cell arranged along the other. Each of the plurality of memory cells includes: a first transistor comprising first and second diffusion layers; a second transistor comprising third and fourth diffusion layers; and a magnetoresistance element having one of terminals thereof connected to an interconnection layer which provides an electrical connection between the second and third diffusion layers. The fourth diffusion layer of the first memory cell is also used as the first diffusion layer of the second memory cell. In addition, the fourth diffusion layer of the second memory cell is also used as the first diffusion layer of the third memory cell.

High-mobility ambipolar transistors and high-gain inverters from a donor-acceptor copolymer semiconductor.

Abstract: Ambipolar organic field-effect transistors (OFETs), which are capable of both p- and n-channel operations, are gaining attention as an alternative approach to mimicking complementary metal-oxide semiconductor (CMOS) digital integrated circuits for achieving high-performance and cost-effective circuits in organic electronics. [1‐13] Low power dissipation and high performance are some of the major advantages of CMOS technology over non-complementary ones. [14] Power consumption is minimized in CMOS circuits because the component transistors are selectively turned on only when the circuit is switching, otherwise they are off at the steady state. The better performance of a CMOS circuit in terms of sharp switching and high noise immunity arises because every elemental transistor actively contributes to the function of the circuit. [14] Most efforts towards CMOS-like circuits in organic electronics have focused on utilizing distinct p- and n-type semiconductors. [1,15] However, the necessity of lateral patterning of semiconductors in CMOS circuits makes device fabrication on a common substrate a very complex process. Ambipolar OFETs represent an approach to high-performance CMOS-like circuits that minimize patterning and complex fabrication processes. [1] Ambipolar transistors are also of interest in fundamental studies of charge transport in organic semiconductors [1,6,16] as well as the development of efficient light-emitting transistors. [8,17‐21]

Ionic/electronic hybrid materials integrated in a synaptic transistor with signal processing and learning functions

Abstract: 2010 WILEY-VCH Verlag Gmb Signal processing, memory, and learning functions are established in the human brain by modifying ionic fluxes in neurons and synapses. Through a synapse, a potential spike signal in a presynaptic neuron can trigger an ionic excitatory postsynaptic current (EPSC) or inhibitory postsynaptic current (IPSC) that temporally lasts for 1–10ms in a postsynaptic neuron. This enables the postsynaptic neuron to collectively process the EPSC or IPSC through 10–10 synapses to establish spatial and temporal correlated functions. The synaptic transmission efficacy can be modified by temporally correlated preand post-synaptic spikes via spike-timing-dependent plasticity (STDP). For example, if a postsynaptic spike is triggered momentarily after a presynaptic spike by a few milliseconds, the synaptic efficacy will be increased, resulting in long-term potentiation (LTP), but if the temporal order is reversed, the synaptic efficacy will be decreased, resulting in long-term depression (LTD). The synaptic efficacy can also be modified with reversed polarities in STDP in different types of synapses. STDP is essential to modify synapses in a neural network for learning and memory functions of the brain. Electronic materials, devices, and circuits have been explored extensively to emulate synapses, but to date they have not been able to match the synaptic functions in the brain. Synaptic transistors with nonvolatile analog memory were fabricated by integrating a charge-storage or ferroelectric materials onto the gate structure of Si metal-oxide-semiconductor (MOS) transistors, but these devices cannot emulate the essential synaptic dynamic functions such as EPSC/IPSC or STDP. Electronic neuromorphic circuits have been designed and fabricated to supply EPSC/IPSC and STDP, but these nonlinear dynamic analog circuits require many transistors and several capacitors to emulate a single synapse. The large capacitor size, complex architecture, and energy consumption of these synaptic circuits limited the number of synapses that could be integrated onto a single chip to about 10–10. The lack of a small, cheap device with the essential synaptic dynamic properties for signal processing, learning, and memory prohibits the circuits from approaching the scale and functions of the human brain that contains 10 synapses. We have designed and fabricated a synaptic transistor based on ionic/electronic hybrid materials by integrating a layer of ionic conductor and a layer of ion-doped conjugated polymer, onto the gate of a Si-based transistor. In analogy to the synapse, a potential spike can trigger ionic fluxes with a temporal lapse of a few milliseconds in the polymer, which in turn spontaneously generates EPSC in the Si layer. Temporally correlated preand post-synaptic spikes can modify ions stored in the polymer, resulting in a nonvolatile strengthening or weakening of the device transmission efficacy with STDP. A single hybrid transistor can replace presently utilized complex and energyconsuming electronic circuits to emulate the synapse for spike signal processing, learning, and memory, which could provide a new pathway to construct neuromorphic circuits approaching the scale and functions of the brain. The synaptic transistor has a Si n-p-n source-channel-drain structure of a conventional MOS transistor, with the Si channel covered by a 3-nm-thick SiO2 insulating layer (Fig. 1a). A 70-nm-thick conjugated polymer layer of poly[2-methoxy-5(20-ethylhexyloxy)-p-phenylene vinylene] (MEH-PPV) and a 70-nm-thick ionic conductive layer of RbAg4I5 were sandwiched between the gate SiO2 insulator and an Al/Ti electrode. To emulate synaptic functions, presynaptic spikes were applied to the transistor gate, and postsynaptic currents, I, were measured from the source. Postsynaptic spikes were also applied to the source. A spike was composed of a 1ms-wide positive voltage pulse with an amplitude Vþ1⁄4 3–5V immediately followed by a 1 ms-wide negative voltage pulse with an amplitude V 1⁄4 3 to 5V (Fig. 1a, Inset). After the spike, the transistor was operated at its rest state under a subthreshold condition by setting the gate voltage Vg1⁄4 0 V. A drain voltage Vd1⁄4 0.1 V was applied continuously. When a presynaptic spike with amplitudes of Vþ/V 1⁄4 4V/ 5V was applied to the transistor gate, the typical I is

Reduced electric field in junctionless transistors

Abstract: The electric field perpendicular to the current flow is found to be significantly lower in junctionless transistors than in regular inversion-mode or accumulation-mode field-effect transistors. Since inversion channel mobility in metal-oxide-semionductor transistors is reduced by this electric field, the low field in junctionless transistor may give them an advantage in terms of current drive for nanometer-scale complementary metal-oxide semiconductor applications. This observation still applies when quantum confinement is present.

Spin Hall effect transistor.

Abstract: The field of semiconductor spintronics explores spin-related quantum relativistic phenomena in solid-state systems. Spin transistors and spin Hall effects have been two separate leading directions of research in this field. We have combined the two directions by realizing an all-semiconductor spin Hall effect transistor. The device uses diffusive transport and operates without electrical current in the active part of the transistor. We demonstrate a spin AND logic function in a semiconductor channel with two gates. Our study shows the utility of the spin Hall effect in a microelectronic device geometry, realizes the spin transistor with electrical detection directly along the gated semiconductor channel, and provides an experimental tool for exploring spin Hall and spin precession phenomena in an electrically tunable semiconductor layer.

Solid-state imaging device, method of manufacturing the same, and electronic apparatus

Abstract: A solid-state imaging device includes: a pixel region in which a plurality of pixels composed of a photoelectric conversion section and a pixel transistor is arranged; an on-chip color filter; an on-chip microlens; and a multilayer interconnection layer in which a plurality of layers of interconnections is formed through an interlayer insulating film. The solid-state imaging device further includes a light-shielding film formed through an insulating layer in a pixel boundary of a light receiving surface in which the photoelectric conversion section is arranged.

A Water‐Gate Organic Field‐Effect Transistor

Abstract: High-dielectric-constant insulators, organic monolayers, and electrolytes have been successfully used to generate organic field-effect transistors operating at low voltages Here, we report on a de

A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply

Abstract: A 60-GHz band, three-stage pseudo-differential power amplifier (PA) is implemented with input and output baluns on-chip. Each stage consists of a neutralized common-source amplifier pair. Neutralization mitigates the intrinsic gate-drain feedback of each transistor for increased power gain and reverse isolation. Shielded transformers couple the gain stages and allow low supply voltage operation. Fabricated in a 65-nm bulk CMOS process, the measured small-signal gain of the 0.13 × 0.41 mm2 PA is 16 dB at 60 GHz with 3-dB bandwidth more than 8.5 GHz, while consuming 50 mW from a 1-V supply. Reverse isolation is better than 42 dB from 55 to 65 GHz. Maximum saturated output power is 11.5 dBm with a peak PAE of 15.2% measured at 62 GHz; from 58 to 65 GHz, the measured PAE is above 10%.

Controllable Shifts in Threshold Voltage of Top‐Gate Polymer Field‐Effect Transistors for Applications in Organic Nano Floating Gate Memory

Abstract: Organic field-effect transistor (FET) memory is an emerging technology with the potential to realize light-weight, low-cost, flexible charge storage media. Here, solution-processed poly[9,9-dioctylfluorenyl-2,7-diyl]-co-(bithiophene)] (F8T2) nano floating gate memory (NFGM) with a top-gate/bottom-contact device configuration is reported. A reversible shift in the threshold voltage (V Th ) and reliable memory characteristics was achieved by the incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative charges (electrons) at the interface between polystyrene and cross-linked poly(4-vinylphenol). The F8T2 NFGM showed relatively high field-effect mobility (μ FET ) (0.02 cm 2 V -1 s -1 ) for an amorphous semiconducting polymer with a large memory window (ca. 30 V), a high on/off ratio (more than 10 4 ) during writing and erasing with an operation voltage of 80 V of gate bias in a relatively short timescale (less than 1 s), and a retention time of a few hours. This top-gated polymer NFGM could be used as an organic transistor memory element for organic flash memory.

It's time to reinvent the transistor!

Abstract: A breakthrough in materials could refresh and sustain the information technology revolution.

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

Abstract: A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-?m 2.5-V standard I/O FETs in a 0.13-?m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.

Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions

Abstract: This paper presents a pseudo-2-D surface potential model for the double-gate tunnel field-effect transistor (DG-TFET). Analytical expressions are derived for the 2-D potential, electric field, and generation rate, and used to numerically extract the tunneling current. The model predicts the device characteristics for a large range of parameters and allows gaining insight on the device physics. The depletion regions induced inside the source and drain are included in the solution, and we show that these regions become critical when scaling the device length. The fringing field effect from the gates on these regions is also included. The validity of the model is tested for devices scaled to 10-nm length with SiO2 and high-? dielectrics by comparison to 2-D finite-element simulations.

Improving polymer transistor performance via morphology control

Abstract: In this tutorial review, different film microstructures, commonly termed morphologies, into which the organic semiconductor polymers self-assemble macroscopically are presented, together with their corresponding influence on charge carrier mobility and hence transistor behaviour. It will be clarified how various chemical design approaches and solution processing methods enable the manipulation of polymer morphology, leading to improvements in transistor performance. Ultimately, it is illustrated that the directional alignment of polymers form oriented fiber-like films, yielding one of the highest mobilities reported so far for polymer transistors. Based on these observations, a prediction is made concerning which kind of morphology is expected to reach the best charge carrier mobility.

Flexible low-voltage organic transistors and circuits based on a high-mobility organic semiconductor with good air stability.

Abstract: Flexible transistors and circuits based on dinaphtho-[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT), a conjugated semiconductor with a large ionization potential (5.4 eV), are reported. The transistors have a mobility of 0.6 cm(2) V-1 s(-1) and the ring oscillators have a stage delay of 18 mu s. Due to the excellent stability of the semiconductor, the devices and circuits maintain 50% of their initial performance for a period of 8 months in ambient air.

Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor

Abstract: Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data.