Showing papers on "Transistor published in 2017"

Highly stretchable polymer semiconductor films through the nanoconfinement effect

Abstract: Soft and conformable wearable electronics require stretchable semiconductors, but existing ones typically sacrifice charge transport mobility to achieve stretchability. We explore a concept based on the nanoconfinement of polymers to substantially improve the stretchability of polymer semiconductors, without affecting charge transport mobility. The increased polymer chain dynamics under nanoconfinement significantly reduces the modulus of the conjugated polymer and largely delays the onset of crack formation under strain. As a result, our fabricated semiconducting film can be stretched up to 100% strain without affecting mobility, retaining values comparable to that of amorphous silicon. The fully stretchable transistors exhibit high biaxial stretchability with minimal change in on current even when poked with a sharp object. We demonstrate a skinlike finger-wearable driver for a light-emitting diode.

Metal-Ion-Modified Black Phosphorus with Enhanced Stability and Transistor Performance.

Abstract: Black phosphorus (BP), a burgeoning elemental 2D semiconductor, has aroused increasing scientific and technological interest, especially as a channel material in field-effect transistors (FETs). However, the intrinsic instability of BP causes practical concern and the transistor performance must also be improved. Here, the use of metal-ion modification to enhance both the stability and transistor performance of BP sheets is described. Ag+ spontaneously adsorbed on the BP surface via cation-π interactions passivates the lone-pair electrons of P thereby rendering BP more stable in air. Consequently, the Ag+ -modified BP FET shows greatly enhanced hole mobility from 796 to 1666 cm2 V-1 s-1 and ON/OFF ratio from 5.9 × 104 to 2.6 × 106 . The mechanisms pertaining to the enhanced stability and transistor performance are discussed and the strategy can be extended to other metal ions such as Fe3+ , Mg2+ , and Hg2+ . Such stable and high-performance BP transistors are crucial to electronic and optoelectronic devices. The stability and semiconducting properties of BP sheets can be enhanced tremendously by this novel strategy.

Li‐Ion Synaptic Transistor for Low Power Analog Computing

Abstract: Nonvolatile redox transistors (NVRTs) based upon Li-ion battery materials are demonstrated as memory elements for neuromorphic computer architectures with multi-level analog states, "write" linearity, low-voltage switching, and low power dissipation. Simulations of backpropagation using the device properties reach ideal classification accuracy. Physics-based simulations predict energy costs per "write" operation of <10 aJ when scaled to 200 nm × 200 nm.

Van der Waals epitaxial growth and optoelectronics of large-scale WSe 2 /SnS 2 vertical bilayer p–n junctions

Abstract: High-quality two-dimensional atomic layered p–n heterostructures are essential for high-performance integrated optoelectronics. The studies to date have been largely limited to exfoliated and restacked flakes, and the controlled growth of such heterostructures remains a significant challenge. Here we report the direct van der Waals epitaxial growth of large-scale WSe2/SnS2 vertical bilayer p–n junctions on SiO2/Si substrates, with the lateral sizes reaching up to millimeter scale. Multi-electrode field-effect transistors have been integrated on a single heterostructure bilayer. Electrical transport measurements indicate that the field-effect transistors of the junction show an ultra-low off-state leakage current of 10−14 A and a highest on–off ratio of up to 107. Optoelectronic characterizations show prominent photoresponse, with a fast response time of 500 μs, faster than all the directly grown vertical 2D heterostructures. The direct growth of high-quality van der Waals junctions marks an important step toward high-performance integrated optoelectronic devices and systems. Growth of large area and defect-free two-dimensional semiconductor layers for high-performance p–n junction applications has been a great challenge. Yang et al. prepare millimeter-scaled WSe2/SnS2 vertical heterojunctions by two-step van der Waals epitaxy, which show excellent optoelectronic properties.

Porous Field-Effect Transistors Based on a Semiconductive Metal-Organic Framework.

Abstract: Recently, the emergence of conductive metal–organic frameworks (MOFs) has given great prospects for their applications as active materials in electronic devices In this work, a high-quality, free-standing conductive MOF membrane was prepared by an air–liquid interfacial growth method Accordingly, field-effect transistors (FETs) possessing a crystalline microporous MOF channel layer were successfully fabricated for the first time The porous FETs exhibited p-type behavior, distinguishable on/off ratios, and excellent field-effect hole mobilities as high as 486 cm2 V–1 s–1, which is even comparable to the highest value reported for solution-processed organic or inorganic FETs

High operational and environmental stability of high-mobility conjugated polymer field-effect transistors through the use of molecular additives.

Abstract: Due to their low-temperature processing properties and inherent mechanical flexibility, conjugated polymer field-effect transistors (FETs) are promising candidates for enabling flexible electronic circuits and displays. Much progress has been made on materials performance; however, there remain significant concerns about operational and environmental stability, particularly in the context of applications that require a very high level of threshold voltage stability, such as active-matrix addressing of organic light-emitting diode displays. Here, we investigate the physical mechanisms behind operational and environmental degradation of high-mobility, p-type polymer FETs and demonstrate an effective route to improve device stability. We show that water incorporated in nanometre-sized voids within the polymer microstructure is the key factor in charge trapping and device degradation. By inserting molecular additives that displace water from these voids, it is possible to increase the stability as well as uniformity to a high level sufficient for demanding industrial applications.

Two-dimensional non-volatile programmable p–n junctions

Abstract: Semiconductor p–n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p–n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p–n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p–n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits. Stable, nonvolatile, programmable 2D p–n junctions enable realization of high-performance memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Modulation-doped β-(Al0.2Ga0.8)2O3/Ga2O3 field-effect transistor

Abstract: Modulation-doped heterostructures are a key enabler for realizing high mobility and better scaling properties for high performance transistors. We report the realization of a modulation-doped two-dimensional electron gas (2DEG) at the β-(Al0.2Ga0.8)2O3/Ga2O3 heterojunction by silicon delta doping. The formation of a 2DEG was confirmed using capacitance voltage measurements. A modulation-doped 2DEG channel was used to realize a modulation-doped field-effect transistor. The demonstration of modulation doping in the β-(Al0.2Ga0.8)2O3/Ga2O3 material system could enable heterojunction devices for high performance electronics.

Modulation-doped beta-(Al0.2Ga0.8)2O3/Ga2O3 Field-Effect Transistor

Abstract: Modulation-doped heterostructures are a key enabler for realizing high mobility and better scaling properties for high performance transistors. We report the realization of modulation-doped two-dimensional electron gas (2DEG) at beta(Al0.2Ga0.8)2O3/ Ga2O3 heterojunction using silicon delta doping. The formation of a 2DEG was confirmed using capacitance voltage measurements. A modulation-doped 2DEG channel was used to realize a modulation-doped field-effect transistor. The demonstration of modulation doping in the beta-(Al0.2Ga0.8)2O3/ Ga2O3 material system could enable heterojunction devices for high performance electronics.

Sustained Sub-60 mV/decade switching via the negative capacitance effect in MoS2 transistors

Abstract: It has been shown that a ferroelectric material integrated into the gate stack of a transistor can create an effective negative capacitance (NC) that allows the device to overcome “Boltzmann tyranny”. While this switching below the thermal limit has been observed with Si-based NC field-effect transistors (NC-FETs), the adaptation to 2D materials would enable a device that is scalable in operating voltage as well as size. In this work, we demonstrate sustained sub-60 mV/dec switching, with a minimum subthreshold swing (SS) of 6.07 mV/dec (average of 8.03 mV/dec over 4 orders of magnitude in drain current), by incorporating hafnium zirconium oxide (HfZrO2 or HZO) ferroelectric into the gate stack of a MoS2 2D-FET. By first fabricating and characterizing metal–ferroelectric–metal capacitors, the MoS2 is able to be transferred directly on top and characterized with both a standard and a negative capacitance gate stack. The 2D NC-FET exhibited marked enhancement in low-voltage switching behavior compared to th...

Ultratransparent and stretchable graphene electrodes

Abstract: Two-dimensional materials, such as graphene, are attractive for both conventional semiconductor applications and nascent applications in flexible electronics. However, the high tensile strength of graphene results in fracturing at low strain, making it challenging to take advantage of its extraordinary electronic properties in stretchable electronics. To enable excellent strain-dependent performance of transparent graphene conductors, we created graphene nanoscrolls in between stacked graphene layers, referred to as multilayer graphene/graphene scrolls (MGGs). Under strain, some scrolls bridged the fragmented domains of graphene to maintain a percolating network that enabled excellent conductivity at high strains. Trilayer MGGs supported on elastomers retained 65% of their original conductance at 100% strain, which is perpendicular to the direction of current flow, whereas trilayer films of graphene without nanoscrolls retained only 25% of their starting conductance. A stretchable all-carbon transistor fabricated using MGGs as electrodes exhibited a transmittance of >90% and retained 60% of its original current output at 120% strain (parallel to the direction of charge transport). These highly stretchable and transparent all-carbon transistors could enable sophisticated stretchable optoelectronics.

Capacitively Coupled Arrays of Multiplexed Flexible Silicon Transistors for Long-Term Cardiac Electrophysiology.

Abstract: Advanced capabilities in electrical recording are essential for the treatment of heart-rhythm diseases. The most advanced technologies use flexible integrated electronics; however, the penetration of biological fluids into the underlying electronics and any ensuing electrochemical reactions pose significant safety risks. Here, we show that an ultrathin, leakage-free, biocompatible dielectric layer can completely seal an underlying layer of flexible electronics while allowing for electrophysiological measurements through capacitive coupling between tissue and the electronics, and thus without the need for direct metal contact. The resulting current-leakage levels and operational lifetimes are, respectively, four orders of magnitude smaller and between two and three orders of magnitude longer than those of any other flexible-electronics technology. Systematic electrophysiological studies with normal, paced and arrhythmic conditions in Langendorff hearts highlight the capabilities of the capacitive-coupling approach. Our technology provides a realistic pathway towards the broad applicability of biocompatible, flexible electronic implants.

High-Performance GaN Vertical Fin Power Transistors on Bulk GaN Substrates

Abstract: This letter reports a GaN vertical fin power field-effect-transistor structure with submicron fin-shaped channels on bulk GaN substrates. In this vertical transistor design only n-GaN layers are needed, while no material regrowth or p-GaN layer is required. A combined dry/wet etch was used to get smooth fin vertical sidewalls. The fabricated transistor demonstrated a threshold voltage of 1 V and specific on resistance of 0.36 ${\mathrm {m}}\Omega {\mathrm {cm}}^{2}$ . By proper electric field engineering, 800 V blocking voltage was achieved at a gate bias of 0 V.

Hysteresis in the transfer characteristics of MoS2 transistors

Abstract: We investigate the origin of the hysteresis observed in the transfer characteristics of back-gated field-effect transistors with an exfoliated MoS2 channel. We find that the hysteresis is strongly enhanced by increasing either gate voltage, pressure, temperature or light intensity. Our measurements reveal a step-like behavior of the hysteresis around room temperature, which we explain as water-facilitated charge trapping at the MoS2/SiO2 interface. We conclude that intrinsic defects in MoS2, such as S vacancies, which result in effective positive charge trapping, play an important role, besides H2O and O2 adsorbates on the unpassivated device surface. We show that the bistability associated to the hysteresis can be exploited in memory devices.

Steep-slope Hysteresis-free Negative Capacitance MoS2 Transistors

Abstract: The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MoS2) 2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack. This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 {\mu}A/{\mu}m, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied.

Comparative Analysis on Conducted CM EMI Emission of Motor Drives: WBG Versus Si Devices

Abstract: Silicon carbide (SiC) MOSFETs and gallium nitride (GaN) high-electron mobility transistors are perceived as future replacements for Si IGBTs and MOSFETs in medium- and low-voltage drives due to their low conduction and switching losses. However, it is widely believed that the already significant conducted common-mode (CM) electromagnetic interference (EMI) emission of motor drives will be further exacerbated by the high-speed switching operation of these new devices. Hence, this paper investigates and quantifies the increase in the conducted CM EMI emission of a pulse width modulation inverter-based motor drive when SiC and GaN devices are adopted. Through an analytical approach, the results reveal that the influence of dv/dt on the conducted CM emission is generally limited. On the other hand, the influence of switching frequency is more significant. Lab tests are also conducted to verify the analysis.

Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

Abstract: In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling.

Carbon nanotube transistors scaled to a 40-nanometer footprint

Abstract: The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density—above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays.

InP HBT Technologies for THz Integrated Circuits

Abstract: Highly scaled indium phosphide (InP) heterojunction bipolar transistor (HBT) technologies have been demonstrated with maximum frequencies of oscillation ( $f_{\max}$ ) of >1 THz and circuit operation has been extended into the lower end of the terahertz (THz) frequency band. InP HBTs offer high radio-frequency (RF) output power density, millivolt (mV) threshold uniformity, and high levels of integration. Integration with multilevel thin-film wiring permits the realization of compact and complex THz monolithic integrated circuits (TMICs). Circuit results reported from InP HBT technologies include: 200-mW power amplifiers at 210 GHz, 670-GHz amplifiers and fundamental oscillators, and fully integrated 600-GHz transmitter circuits. We review the state of the art in THz-capable InP HBT devices and integrated circuit (IC) technologies. Challenges in extending transistor bandwidth and in circuit design at THz frequencies will also be addressed.

β-Ga2O3 on insulator field-effect transistors with drain currents exceeding 1.5 A/mm and their self-heating effect

Abstract: We have demonstrated that depletion/enhancement-mode β-Ga2O3 on insulator field-effect transistors can achieve a record high drain current density of 1.5/1.0 A/mm by utilizing a highly doped β-Ga2O3 nano-membrane as the channel. β-Ga2O3 on insulator field-effect transistor (GOOI FET) shows a high on/off ratio of 1010 and low subthreshold slope of 150 mV/dec even with 300 nm thick SiO2. The enhancement-mode GOOI FET is achieved through surface depletion. An ultra-fast, high resolution thermo-reflectance imaging technique is applied to study the self-heating effect by directly measuring the local surface temperature. High drain current, low Rc, and wide bandgap make the β-Ga2O3 on insulator field-effect transistor a promising candidate for future power electronics applications.

Room temperature multiplexed gas sensing using chemical-sensitive 3.5-nm-thin silicon transistors

Abstract: There is great interest in developing a low-power gas sensing technology that can sensitively and selectively quantify the chemical composition of a target atmosphere. Nanomaterials have emerged as extremely promising candidates for this technology due to their inherent low-dimensional nature and high surface-to-volume ratio. Among these, nanoscale silicon is of great interest because pristine silicon is largely inert on its own in the context of gas sensing, unless functionalized with an appropriate gas-sensitive material. We report a chemical-sensitive field-effect transistor (CS-FET) platform based on 3.5-nm-thin silicon channel transistors. Using industry-compatible processing techniques, the conventional electrically active gate stack is replaced by an ultrathin chemical-sensitive layer that is electrically nonconducting and coupled to the 3.5-nm-thin silicon channel. We demonstrate a low-power, sensitive, and selective multiplexed gas sensing technology using this platform by detecting H2S, H2, and NO2 at room temperature for environment, health, and safety in the oil and gas industry, offering significant advantages over existing technology. Moreover, the system described here can be readily integrated with mobile electronics for distributed sensor networks in environmental pollution mapping and personal air-quality monitors.

A Charge-Plasma-Based Dielectric-Modulated Junctionless TFET for Biosensor Label-Free Detection

Abstract: To reduce the fabrication complexity and cost of the nanoscale devices, a charge-plasma concept is introduced for the first time to implement a dielectric-modulated junctionless tunnel field-effect transistor (DM-JLTFET) for biosensor label-free detection. The formation of p+ source and n+ drain regions in DM-JLTFET is done by the deposition of platinum (work function = 5.93 eV) and hafnium (work function = 3.9 eV) materials, respectively, over the silicon body. Furthermore, a nanogap cavity embedded within the gate dielectric is created by etching the portion of gate oxide layer toward the source end for sensing biomolecules. For this, the sensing capability of DM-JLTFET has been investigated in terms of variation in dielectric constant, charge density, length, and thickness of the cavity at different bias conditions. Finally, a comparative study between DM-JLTFET and MOSFET biosensor is investigated. The implementation of proposed device and all the simulations have been performed by using ATLAS device simulator.

Organic light emitting display

Abstract: An organic light emitting display includes a driving transistor, an organic light emitting diode, an interlayer insulating layer, and a connection electrode. The interlayer insulating layer covers the driving transistor, and first and second via holes are formed in the interlayer insulating layer. The organic light emitting diode is on the interlayer insulating layer and connected to the driving transistor. The connection electrode is on the interlayer insulating layer and connected to an auxiliary line through the second via hole. The connection electrode surrounds a portion of the interlayer insulating layer together with the auxiliary line. The organic light emitting diode includes an anode connected to the driving transistor through the first via hole, an organic light emitting layer on the anode, and a cathode on the organic light emitting layer and connected to the auxiliary line through the connection electrode.

Superior Plasmonic Photodetectors Based on Au@MoS2 Core-Shell Heterostructures.

Abstract: Integrating plasmonic materials into semiconductor media provides a promising approach for applications such as photosensing and solar energy conversion The resulting structures introduce enhanced light–matter interactions, additional charge trap states, and efficient charge-transfer pathways for light-harvesting devices, especially when an intimate interface is built between the plasmonic nanostructure and semiconductor Herein, we report the development of plasmonic photodetectors using Au@MoS2 heterostructures—an Au nanoparticle core that is encapsulated by a CVD-grown multilayer MoS2 shell, which perfectly realizes the intimate and direct interfacing of Au and MoS2 We explored their favorable applications in different types of photosensing devices The first involves the development of a large-area interdigitated field-effect phototransistor, which shows a photoresponsivity ∼10 times higher than that of planar MoS2 transistors The other type of device geometry is a Si-supported Au@MoS2 heterojuncti

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films

Abstract: Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units...

\b{eta}-Ga2O3 on Insulator Field-effect Transistors with Drain Currents Exceeding 1.5 A/mm and Their Self-heating Effect

Abstract: We have demonstrated that depletion/enhancement-mode b-Ga2O3 on insulator field-effect transistors can achieve a record high drain current density of 1.5/1.0 A/mm by utilizing a highly doped b-Ga2O3 nano-membrane as the channel. b-Ga2O3 on insulator field-effect transistor (GOOI FET) shows a high on/off ratio of 1010 and low subthreshold slope of 150 mV/dec even with 300 nm thick SiO2. The enhancement-mode GOOI FET is achieved through surface depletion. An ultra-fast, high resolution thermo-reflectance imaging technique is applied to study the self-heating effect by directly measuring the local surface temperature. High drain current, low Rc, and wide bandgap make the b-Ga2O3 on insulator field-effect transistor a promising candidate for future power electronics applications.

Analyzing the Carrier Mobility in Transition-metal Dichalcogenide MoS2 Field-effect Transistors

Abstract: Transition-metal dichalcogenides (TMDCs) are important class of two-dimensional (2D) layered materials for electronic and optoelectronic applications, due to their ultimate body thickness, sizable and tunable bandgap, and decent theoretical room-temperature mobility of hundreds to thousands cm2/Vs. So far, however, all TMDCs show much lower mobility experimentally because of the collective effects by foreign impurities, which has become one of the most important limitations for their device applications. Here, taking MoS2 as an example, we review the key factors that bring down the mobility in TMDC transistors, including phonons, charged impurities, defects, and charge traps. We introduce a theoretical model that quantitatively captures the scaling of mobility with temperature, carrier density and thickness. By fitting the available mobility data from literature over the past few years, we are able to obtain the density of impurities and traps for a wide range of transistor structures. We show that interface engineering such as oxide surface passivation, high-k dielectrics and BN encapsulation could effectively reduce the impurities, leading to improved device performances. For few-layer TMDCs, we analytically model the lopsided carrier distribution to elucidate the experimental increase of mobility with the number of layers. From our analysis, it is clear that the charge transport in TMDC samples is a very complex problem that must be handled carefully. We hope that this Review can provide new insights and serve as a starting point for further improving the performance of TMDC transistors.

Delta-doped β-gallium oxide field-effect transistor

Abstract: We report silicon delta doping in gallium oxide (β-Ga2O3) grown by plasma-assisted molecular beam epitaxy using a shutter pulsing technique. We describe the growth procedures that can be used to realize high Si incorporation in an oxidizing oxygen plasma environment. Delta doping was adopted to realize thin (12 nm) low-resistance layers with a sheet resistance of 320 Ω/square (mobility of 83 cm2 V−1 s−1, integrated sheet charge of 2.4 × 1014 cm−2). A single delta-doped sheet of carriers was employed as a channel to realize a field-effect transistor with current I D,max = 236 mA/mm and transconductance g m = 26 mS/mm.

Solution‐Processed Nanoporous Organic Semiconductor Thin Films: Toward Health and Environmental Monitoring of Volatile Markers

Abstract: Porous materials are ubiquitous in nature and have found a wide range of applications because of their unique absorption, optical, mechanical, and catalytic properties. Large surface-area-to-volume ratio is deemed a key factor contributing to their catalytic properties. Here, it is shown that introducing tunable nanopores (50–700 nm) to organic semiconductor thin films enhances their reactivity with volatile organic compounds by up to an order of magnitude, while the surface-area-to-volume ratio is almost unchanged. Mechanistic investigations show that nanopores grant direct access to the highly reactive sites otherwise buried in the conductive channel of the transistor. The high reactivity of nanoporous organic field-effect transistors leads to unprecedented ultrasensitive, ultrafast, selective chemical sensing below the 1 ppb level on a hundred millisecond time scale, enabling a wide range of health and environmental applications. Flexible sensor chip for monitoring breath ammonia is further demonstrated; this is a potential biomarker for chronic kidney disease.

In-plane Schottky-barrier field-effect transistors based on 1 T /2 H heterojunctions of transition-metal dichalcogenides

Abstract: As Moore's law approaches its end, two-dimensional (2D) materials are intensely studied for their potentials as one of the ``More than Moore' (MM) devices. However, the ultimate performance limits and the optimal design parameters for such devices are still unknown. One common problem for the 2D-material-based device is the relative weak on-current. In this study, two-dimensional Schottky-barrier field-effect transistors (SBFETs) consisting of in-plane heterojunctions of 1T metallic-phase and 2H semiconducting-phase transition-metal dichalcogenides (TMDs) are studied following the recent experimental synthesis of such devices at a much larger scale. Our ab initio simulation reveals the ultimate performance limits of such devices and offers suggestions for better TMD materials. Our study shows that the Schottky-barrier heights (SBHs) of the in-plane 1T/2H contacts are smaller than the SBHs of out-of-plane contacts, and the contact coupling is also stronger in the in-plane contact. Due to the atomic thickness of the monolayer TMD, the average subthreshold swing of the in-plane TMD-SBFETs is found to be close to the limit of 60 mV/dec, and smaller than that of the out-of-plane TMD-SBFET device. Different TMDs are considered and it is found that the in-plane $\mathrm{WT}{\mathrm{e}}_{2}\text{\ensuremath{-}}\mathrm{SBFET}$ provides the best performance and can satisfy the performance requirement of the sub-10-nm high-performance transistor outlined by the International Technology Roadmap for Semiconductors, and thus could be developed into a viable sub-10-nm MM device in the future.