J
Jong-Ho Lee
Researcher at Seoul National University
Publications - 1054
Citations - 14204
Jong-Ho Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: Field-effect transistor & Threshold voltage. The author has an hindex of 45, co-authored 928 publications receiving 11335 citations. Previous affiliations of Jong-Ho Lee include Massachusetts Institute of Technology & Kyungpook National University.
Papers
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Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors
TL;DR: In this paper, the experimental and modeling study of bias-stress-induced threshold voltage instabilities in amorphous indium-gallium-zinc oxide thin film transistors is reported.
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Depressive behaviors and decreased expression of serotonin reuptake transporter in rats that experienced neonatal maternal separation
Jong-Ho Lee,Hyungjin Kim,Hyungjin Kim,Jae Goo Kim,Jae Goo Kim,Vitaly Ryu,Bom-Taeck Kim,Dong-Won Kang,Jeong Won Jahng +8 more
TL;DR: It is suggested that neonatal maternal separation may result in the development of depression- and/or anxiety-like behaviors in later life, in which the long-term alterations in 5-HTergic neurotransmission may take a role.
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Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory
Jang-Gn Yun,Garam Kim,Joung-Eob Lee,Yoon Kim,Wonbo Shim,Jong-Ho Lee,Hyungcheol Shin,Jong Duk Lee,Byung-Gook Park +8 more
TL;DR: In this paper, a 3D NAND flash memory array with multiple single-crystal Si nanowires is investigated, where the array structure and fabrication process are described, including the electrical isolation of stacked nanwires.
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Three-dimensional imaging of individual hafnium atoms inside a semiconductor device
Klaus van Benthem,Andrew R. Lupini,Miyoung Kim,Hionsuck Baik,SeokJoo Doh,Jong-Ho Lee,Mark P. Oxley,Scott D. Findlay,Leslie J. Allen,Julia T. Luck,Stephen J. Pennycook +10 more
TL;DR: In this paper, a three-dimensional reconstruction of the Hf atom sites, representing a 3D map of potential breakdown sites within the gate dielectric, was demonstrated from a through-focal series of images.
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Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray
Yoon Kim,Jang-Gn Yun,Se Hwan Park,Wandong Kim,Joo Yun Seo,Myounggon Kang,Kyung-Chang Ryoo,Jeong-Hoon Oh,Jong-Ho Lee,Hyungcheol Shin,Byung-Gook Park +10 more
TL;DR: Various critical issues related with 3-D stacked nand Flash memory are examined in this paper and for the first time the structure and operation methods of the “full” array are considered.