Showing papers by "STMicroelectronics published in 2005"

SPIRAL: Code Generation for DSP Transforms

Abstract: Fast changing, increasingly complex, and diverse computing platforms pose central problems in scientific computing: How to achieve, with reasonable effort, portable optimal performance? We present SPIRAL, which considers this problem for the performance-critical domain of linear digital signal processing (DSP) transforms. For a specified transform, SPIRAL automatically generates high-performance code that is tuned to the given platform. SPIRAL formulates the tuning as an optimization problem and exploits the domain-specific mathematical structure of transform algorithms to implement a feedback-driven optimizer. Similar to a human expert, for a specified transform, SPIRAL "intelligently" generates and explores algorithmic and implementation choices to find the best match to the computer's microarchitecture. The "intelligence" is provided by search and learning techniques that exploit the structure of the algorithm and implementation space to guide the exploration and optimization. SPIRAL generates high-performance code for a broad set of DSP transforms, including the discrete Fourier transform, other trigonometric transforms, filter transforms, and discrete wavelet transforms. Experimental results show that the code generated by SPIRAL competes with, and sometimes outperforms, the best available human tuned transform library code.

Review on high-k dielectrics reliability issues

Abstract: High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.

The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance

Abstract: The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is accelerating introduction of new technologies to extend complementary MOS (CMOS) down to, and perhaps beyond, the 22-nm node This acceleration simultaneously requires the industry to intensify research on two highly challenging thrusts: one is scaling CMOS into an increasingly difficult manufacturing domain well below the 90-nm node for high performance (HP), low operating power (LOP), and low standby power (LSTP) applications, and the other is an exciting opportunity to invent fundamentally new approaches to information and signal processing to sustain functional scaling beyond the domain of CMOS This article is focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures This paper provides a brief introduction to each of the new nonclassical CMOS structures This is followed by a presentation of one scenario for introduction of new structural changes to the MOSFET to scale CMOS to the end of the ITRS A brief review of electrostatic scaling of a MOSFET necessary to manage short channel effects (SCEs) at the most advanced technology nodes is also provided

An asynchronous NOC architecture providing low latency service and its multi-level design framework

Abstract: The demands of scalable, low latency and power efficient system-on-chip interconnect cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a new asynchronous network-on-chip (NOC) architecture which provides low latency transfers. This architecture is implemented as a GALS system, where chip units are built as synchronous islands, connected together using a delay insensitive asynchronous network-on-chip topology. The proposed NOC protocol and its asynchronous implementation are presented as well as the multi-level modeling approach using SystemC language and transaction-level-modeling. Preliminary simulation results show that the asynchronous NOC can offer 5 Gbytes/s throughput in a 0.13 /spl mu/m CMOS technology.

30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits

Abstract: Silicon planar and three-dimensional inductors and transformers were designed and characterized on-wafer up to 100 GHz. Self-resonance frequencies (SRFs) beyond 100 GHz were obtained, demonstrating for the first time that spiral structures are suitable for applications such as 60-GHz wireless local area network and 77-GHz automotive RADAR. Minimizing area over substrate is critical to achieving high SRF. A stacked transformer is reported with S/sub 21/ of -2.5 dB at 50 GHz, and which offers improved performance and less area (30 /spl mu/m/spl times/30 /spl mu/m) than planar transformers or microstrip couplers. A compact inductor model is described, along with a methodology for extracting model parameters from simulated or measured y-parameters. Millimeter-wave SiGe BiCMOS mixer and voltage-controlled-oscillator circuits employing spiral inductors are presented with better or comparable performance to previously reported transmission-line-based circuits.

Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof

Abstract: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner

Abstract: A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13-/spl mu/m CMOS process. The chip has an active area of 1.8 mm/sup 2/ with the entire RF portion operated from 1.2 V and the low frequency portion operated from 2.5 V. Its key features are a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner and an high I-Q accuracy quadrature VCO. Measured noise figure is 3.5 dB with an 1/f noise corner of 200 kHz, and an IIP3 of -2 dBm. The synthesizer DSB phase noise integrated over a 10 MHz band is less than -36 dBc while its I-Q phase unbalance is below 1 degree.

AES power attack based on induced cache miss and countermeasure

Abstract: This paper presents a new attack against a software implementation of the Advanced Encryption Standard. The attack aims at flushing elements of the SBOX from the cache, thus inducing a cache miss during the encryption phase. The power trace is then used to detect when the cache miss occurs; if the miss happens in the first round of the AES then the information can be used to recover part of the secret key. The attack has been simulated using the Wattch simulation framework and a simple software implementation of AES (using a single table for the SBOX). The attack can be easily extended to more sophisticated versions of AES with more than one table. Eventually, we present a simple countermeasure which does not require randomization.

Bonded planar double-metal-gate NMOS transistors down to 10 nm

Abstract: Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.

Chemical vapour etching of Si, SiGe and Ge with HCl; applications to the formation of thin relaxed SiGe buffers and to the revelation of threading dislocations

Abstract: We have studied the etching of silicon, SiGe and germanium layers with gaseous HCl in reduced pressure-chemical vapour deposition (RP-CVD). We have observed the occurrence of two etch regimes depending on the etching temperature. The first regime takes place at high temperatures and is characterized by low activation energies (~7 kcal mol−1), this whatever the germanium content of the etched layer. The other regime occurs at low temperatures and has associated high activation energies (which strongly depend upon the germanium concentration of the etched layer: 86 kcal mol−1 for pure Si versus 28 kcal mol−1 for pure Ge). Modifying the HCl partial pressure has different effects depending on the regime. In the high temperature regime, increasing the HCl partial pressure will almost quadratically increase the etch rate (ER ∝ PHCl1.76), this both for Si and Si0.67Ge0.33. Meanwhile, the dependence is sub-linear in the low temperature regime (Si ER ∝ PHCl0.53 and Si0.67Ge0.33 ER ∝ PHCl0.82). The temperature where the regime shifts from one to the other decreases when the Ge concentration increases. To illustrate the added value of the chemical vapour etching, we have demonstrated two possible applications. The first one is the realization of SiGe thin strain relaxed buffers (TSRBs) in the active areas of shallow trench isolation (STI) patterned wafers after etching away the silicon with HCl. We have observed the occurrence of some etching loading effects when moving from a blanket to a patterned wafer. The SiGe TSRBs exhibit some good structural properties (rms roughness of 0.12 nm, no defects observed in cross-sectional transmission electron microscopy). However, they are not fully relaxed and facets are present at the STI/epitaxial stack boundary, signifying they are still not mature enough to be integrated in a metal oxide semiconductor technology. Another possible application is to decorate through some in situ HCl etching the dislocations threading through SiGe relaxed thick layers, with some significant advantages over commonly used wet etching solutions such as the Secco and the Schimmel ones.

SUCCESS-HPON: A next-generation optical access architecture for smooth migration from TDM-PON to WDM-PON

Abstract: Optical access networks are considered to be a definite solution to the problem of upgrading current congested access networks to ones capable of delivering future broadband integrated services. However, the high deployment and maintenance cost of traditional point-to-point architectures is a major economic barrier. Current TDM-PON architectures are economically feasible, but bandwidth-limited. In this article we first discuss the possible role of WDM in access networks and investigate the associated issues. We then present the Stanford University Access Hybrid WDM/TDM Passive Optical Network (SUCCESS-HPON), a next-generation hybrid WDM/TDM optical access architecture that focuses on providing a smooth migration path from current TDM-PONs to future WDM-PONs. The first testbed for this architecture is described, along with the experimental results obtained, including feasibility of bidirectional transmission on the same wavelength on the same fiber for access networks and ONU modulation of upstream data on continuous waves provided by the OLT, eliminating the need for tunable components at the ONUs. The development of a second testbed and the issues it will address, including the implementability of the SUCCESS-HPON MAC protocol and scheduling algorithms, are also described.

4-Mb MOSFET-selected /spl mu/trench phase-change memory experimental chip

Abstract: A /spl mu/trench Phase-Change Memory (PCM) cell with MOSFET selector and its integration in a 4-Mb experimental chip fabricated in 0.18-/spl mu/m CMOS technology are presented. A cascode bitline biasing scheme allows read and write voltages to be fed to the addressed storage elements with the required accuracy. The high-performance capabilities of PCM cells were experimentally investigated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to NOR Flash memories. Programmed cell current distributions on the 4-Mb array demonstrate an adequate working window and, together with first endurance measurements, assess the feasibility of PCMs in standard CMOS technology with few additional process modules.

Multi-objective design space exploration of embedded systems

Abstract: In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized embedded systems. The exploration problem is multi-objective (e.g., energy and delay), so the main goal of this work is to find a good approximation of the Pareto-optimal configurations representing the best energy/delay trade-offs by varying the architectural parameters of the target system. In particular, the paper presents a Design Space Exploration (DSE) framework to simulate the target system and to dynamically profile the target applications. In the proposed DSE framework, a set of heuristic algorithms have been analyzed to reduce the overall exploration time by computing an approximated Pareto set of configurations with respect to the selected figures of merit. Once the approximated Pareto set has been built, the designer can quickly select the best system configuration satisfying the constraints. Experimental results, derived from the application of the proposed DSE framework to a superscalar architecture, show that the exploration time can be reduced by three orders of magnitude with respect to the full search approach, while maintaining a good level of accuracy.

LED driving device with variable light intensity

Abstract: In a device for driving LEDs with variable light intensity, a supply stage has a first operating mode, in which a controlled supply current is generated, and a second operating mode, in which a controlled supply voltage is generated. A LED is connected to the supply stage, receives the controlled supply current or voltage, and has a turning-on threshold voltage higher than the controlled supply voltage. A current sensor generates a current-feedback signal that is correlated to the current flowing in the LED and is supplied to the supply stage in the first operating mode. An intensity-control stage generates a mode-control signal that is sent to the supply stage and controls sequential switching between the first and the second operating modes of the supply stage.

Evolution of materials technology for stacked-capacitors in 65 nm embedded-DRAM

Abstract: The architecture, materials choice and process technology for stacked-capacitors in embedded-DRAM applications are a crucial concern for each new technology node. An overview of the evolution of capacitor technology is presented from the early days of planar PIS (poly/insulator/silicon) capacitors to the MIM (metal/insulator/metal) capacitors used for todays 65 nm technology node. In comparing Ta2O5, HfO2 and Al2O3 as high-k dielectric for use in 65 nm eDRAM technology, Al2O3 is found to give a good compromise between capacitor performance and manufacturability. The use of atomic layer deposition (ALD) is identified to be an enabling technology for both high-k dielectrics and capacitor electrodes. � 2005 Elsevier Ltd. All rights reserved.

Method and system for communicating video data in a packet-switched network, related network and computer program product therefor

Abstract: A method for communicating video data on a wireless channel in a packet-switched network includes the steps of operating at a wireless terminal a compression in packets on the video data during a video coding operation, detecting wireless channel conditions and adapting control parameters of the video coding operation to the detected wireless channel conditions. The compression operation is a robust header compression operation and the step of adapting control parameters of said video coding operation is performed in dependence of information about the wireless channel conditions detected on a feedback channel made available in a decompression step associated with the compression operation.

Free-fall detection device and free-fall protection system for a portable electronic apparatus

Abstract: In an integrated free-fall detection device for a portable apparatus an acceleration sensor generates acceleration signals correlated to the components of the acceleration of the portable apparatus along three detection axes. A dedicated purely hardware circuit connected to the acceleration sensor generates a free-fall detection signal in a continuous way and in real-time. The free-fall detection signal has a first logic value in the event that the acceleration signals are simultaneously lower than a respective acceleration threshold, and is sent to a processor unit of the portable apparatus as an interrupt signal to activate appropriate actions of protection for the portable apparatus. Preferably, the acceleration sensor and the dedicated purely hardware circuit are integrated in a single chip and the acceleration sensor is made as a MEMS.

A SoC Design Methodology Involving a UML 2.0 Profile for SystemC

Abstract: In this paper, we present a SoC design methodology joining the capabilities of UML and SystemC to operate at system-level. We present a UML 2.0 profile of the SystemC language, exploiting the MDA capabilities of defining modeling languages, platform independent and reducible to platform dependent languages. The UML profile captures both the structural and the behavioral features of the SystemC language, and allows high level modeling of system-on-a-chip with straightforward translation to SystemC code.

Synchronization in power-law networks.

Abstract: We consider realistic power-law graphs, for which the power-law holds only for a certain range of degrees. We show that synchronizability of such networks depends on the expected average and expected maximum degree. In particular, we find that networks with realistic power-law graphs are less synchronizable than classical random networks. Finally, we consider hybrid graphs, which consist of two parts: a global graph and a local graph. We show that hybrid networks, for which the number of global edges is proportional to the number of total edges, almost surely synchronize.

A new MAC construction alred and a specific instance ALPHA-MAC

Abstract: We present a new way to construct a MAC function based on a block cipher. We apply this construction to AES resulting in a MAC function that is a factor 2.5 more efficient than CBC-MAC with AES, while providing a comparable claimed security level.

SiOxFy passivation layer in silicon cryoetching

Abstract: The SiOxFy passivation layer created on structure sidewalls during silicon cryoetching is investigated. This SiOxFy passivation layer formation strongly depends on O2 content, temperature and bias. It is a fragile layer, which mostly disappears when the wafer is warmed up to ambient temperature. A mass spectrometer was used to analyze the desorbed species during the warm-up and using this instrument allowed us to find a large signal increase in SiF3+ between −80°C and −50°C. SiF4 etching products can participate in the formation of the passivation layer as it is shown by a series of test experiments. SiF4∕O2 plasmas are used to form a thin SiOxFy layer on a cooled silicon wafer. Thickness and optical index of this thin film can be determined by in situ spectroscopic ellipsometry. It is shown that the passivation layer spontaneously desorbs when the silicon wafer temperature increases in good agreement with the mass spectrometry analysis. Two physical mechanisms are proposed to explain the SiOxFy passivati...

A G/sub m/-C low-pass filter for zero-IF mobile applications with a very wide tuning range

Abstract: A third-order G/sub m/-C Butterworth low-pass filter implementing G/sub m/-tuning and G/sub m/-switching to maximize the tuning range is described. This filter is intended to be used as a channel-selection/anti-aliasing filter in the analog baseband part of a zero-IF radio receiver architecture for multimode mobile communications. Its G/sub m/-switching feature allows extending the tuning range and adapting the power consumption. The filter's cutoff frequency ranges from 50 kHz to 2.2 MHz. An Input IP3 of up to +18 dBV/sub p/ is achieved, for a total worst-case power consumption of 7.3 mW for both I and Q paths, and an effective area of less than 0.5 mm/sup 2/ in a 0.25-/spl mu/m SiGe BiCMOS process. A new figure of merit is introduced for comparison of published low-pass tunable filters including noise, linearity, and tuning range.

SET and RESET pulse characterization in BJT-selected phase-change memories

Abstract: This paper presents program pulse characterization in an 8-Mb BJT-selected phase-change memory test chip. Experimental results of the impact of the bit-line resistance over programming pulse efficiency are provided. Furthermore, in order to compensate for spreads in cell physical parameters in an array portion, a non-conventional staircase-down program pulse is proposed and experimentally evaluated.

Method and apparatus for parallel processing of in-loop deblocking filter for H.264 video compression standard

Abstract: A parallel deblocking filtering method, and deblocking filter processor performing such deblocking, for removing edge artifacts created during video compression. The method includes loading luma samples for a macroblock. Filtering is performed on a set of vertical edges of the macroblock using information in the luma samples, with vertical edge filtering occurring concurrently with the loading of the luma samples. The method also includes filtering a set of horizontal edges of the macroblock using information in the luma samples. The horizontal edge filtering occurs in parallel with vertical edge sampling and with loading operations. The use of parallel and concurrent operations significantly enhances the efficiency of the deblocking method. Storing of filtered samples is also performed in the method, and this storing is performed concurrently with some loading operations as well as filtering operations. Edge filtering includes performing filtering to the H.264 standard and its deblocking filtering algorithm.

Method for multilevel programming of phase change memory cells using a percolation algorithm

Abstract: A method and apparatus for programming a phase change memory cell (2) is disclosed. A phase change memory cell (2) includes a memory element (10) of a phase change material having a first state ("11"), in which the phase change material is crystalline and has a minimum resistance level, a second state ("00") in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states with resistance levels there between. The method includes using programming pulses to program the phase change memory cell (2) in either the set, reset, or one of the intermediate states. To program in the intermediate states, a programming pulse creates a crystalline percolation path having an average diameter (D) through amorphous phase change material and a second programming pulse modifies the diameter (D) of the crystalline percolation path to program the phase change memory cell to the proper current level.

Pinapa: an extraction tool for SystemC descriptions of systems-on-a-chip

Abstract: SystemC is becoming a de-facto standard for the description of complex systems-on-a-chip. It enables system-level descriptions of SoCs: the same language is used for the description of the architecture, software and hardware parts.A tool like Pinapa is compulsory to work on realistic SoCs designs for anything else than simulation: it is able to extract both architecture and behavior information from SystemC code, with very few limitations. Pinapa can be used as a front-end for various analysis tools, ranging from "superlint" to model-checking. It is open source and available from http://greensocs.sourceforge.net/pinapa/. There exists no equivalent tool for SystemC up to now.