Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
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TLDR
In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.Abstract:
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.read more
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Journal ArticleDOI
Carrier mobility characteristics of (100), (110), and (551) oriented atomically flattened Si surfaces for fin structure design of multi-gate metal–insulator–silicon field-effect transistors
TL;DR: In this paper, the carrier mobility characteristics of (100), (110), and (551) oriented atomically flattened Si surfaces for the fin structure design of multi-gate metal-insulator-silicon FETs were reported.
Journal ArticleDOI
Doping profile optimisation in bulk FinFET channel and source/drain extension regions for low off–state leakage
TL;DR: In this paper, the effects of channel and source/drain extension doping profile on these three leakage currents in bulk n-FinFETs with triangular shaped fins were studied. And the optimisation of PTSL implant and anneal conditions, the optimised n-finFET exhibits superior short channel control, <65 mV/dec sub-threshold slope and <20 mV /V DIBL, and extremely low off-state leakage, <30 pA/um.
Proceedings ArticleDOI
Stack gate technique for minimizing leakage current in multigate MOSFETs
TL;DR: In this article, a stack gate technique to suppress the leakage current is proposed with a gate length of 10nm and the performance characteristics are analyzed through ON current, OFF current, Ion/Ioff ratio, DIBL (Drain Induced Barrier Lowering), and SS (subthreshold slope) through 3-D TCAD simulation, metal gates are shown to be feasible.
Proceedings ArticleDOI
Improving the topography performance of ion implantation resist
TL;DR: In this paper, the resist image intensity among the fin and gates can be improved by increasing the thickness of the oxide on the edge of the gate, which is demonstrated from the simulations with the lithography simulator PROLITH.
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