Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
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TLDR
In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.Abstract:
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.read more
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Proceedings ArticleDOI
Circuit architecture and measurement technique to reduce the leakage current stemming from peripheral circuits with an array structure in examining the resistive element
TL;DR: In this paper, a circuit architecture and measurement technique are proposed to reduce the leakage current that passes through peripheral circuits when examining arrays of resistive elements, with the aid of circuit simulations, that can be realized with the stacked column-selection array and the addition of a leakage control terminal.
Proceedings ArticleDOI
Low-voltage organic field-effect transistors for flexible electronics
Ute Zschieschang,Reinhold Rödel,Ulrike Kraft,Kazuo Takimiya,Tarek Zaki,Florian Letzkus,Jörg Butschke,Harald Richter,Joachim N. Burghartz,Wei Xiong,Boris Murmann,Hagen Klauk +11 more
TL;DR: In this paper, a process for the fabrication of bottom-gate, top-contact (inverted staggered) organic thin-film transistors (TFTs) with channel lengths as short as 1 μm on flexible plastic substrates has been developed.
Journal ArticleDOI
Thermal Modeling of Ultraviolet Nanoimprint Lithography
Bhavik C. Patel,Ankur Jain +1 more
TL;DR: In this paper, a numerical simulation model of the nano-printing process was developed to study the effect of various geometrical parameters on the accuracy and throughput of the process.
Dissertation
Modelling and simulation study of NMOS Si nanowire transistors
TL;DR: In this paper, a model-based performance evaluation of vertically-stacked lateral nanowire transistors (NWTs) was carried out using the Ensemble Monte Carlo approach with Poisson-Schrodinger (PS) quantum corrections.
Journal ArticleDOI
Constant voltage stress characterization of nFinFET transistor during total ionizing dose experiment
Bo Li,Yunbo Huang,Jun Wu,Qian Zhang,Liuqing Yang,F. Wan,Jingdong Luo,Zhengsheng Han,Huiyong Yin +8 more
TL;DR: Experimental results show that both effects can cause the threshold voltage of the transistor to shift towards positive, and compared with TID-induced degradation, the devices appear relatively robust against CVS.
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