Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
Reads0
Chats0
TLDR
In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.Abstract:
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.read more
Citations
More filters
Proceedings ArticleDOI
Optimization processing unit (OPU) applied to integrated circuit design and manufacturing
Don C. L. Chen,Tzeng Jiann-Tyng,David B. Scott,S. W. Peng,M. H. Shen,K. T. Sio,Praneeth Narayanasetti +6 more
TL;DR: This paper demonstrates OPU can handle all the field parameter optimization by its very nature, and verified and reduced to practice through performance estimation of circuits for various transistor device indexes by using the BSIM4 and BSIM-CMG modeling optimization system.
Journal ArticleDOI
Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor
TL;DR: In this article, the junctionless mode (JL) and low power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure.
Proceedings ArticleDOI
Diameter Scaling in III-V Gate-All-Around Transistor for Different Cross-Sections
TL;DR: In this paper, the authors explore the impact of channel area scaling in InGaAs gate-all-around transistor for circular (CNW), square (SNW) and triangular (TNW) cross-sections using coupled selfconsistent Schrodinger-Poisson solver.
Book ChapterDOI
Understanding the FinFET Mobility by Systematic Experiments
TL;DR: In this article, the impact of surface orientation, strain, fin doping, and gate stack on SOI double-gate FinFET mobility is systematically investigated, and the experimental results in this chapter suggest that the (110)/ Si FinFets conventionally built on standard (100) wafers offer simultaneously high electron and hole mobility, which can be further improved by tensile and compressive stress, respectively.
Journal ArticleDOI
High-performance logic transistor DC benchmarking toward 7 nm technology-node between III–V and Si tri-gate n-MOSFETs using virtual-source injection velocity model
TL;DR: In this article, the authors report on Virtual-Source (VS) based analytical and physical model, which was calibrated by using state-of-the-art experimental data on III-V and Si tri-gate n-MOSFET, aiming to compare High-Performance (HP) logic transistor performance at 7nm technology-node.
Related Papers (5)
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
C. Auth,C. Allen,A. Blattner,Daniel B. Bergstrom,Mark R. Brazier,M. Bost,M. Buehler,V. Chikarmane,Tahir Ghani,Timothy E. Glassman,R. Grover,W. Han,D. Hanken,Michael L. Hattendorf,P. Hentges,R. Heussner,J. Hicks,D. Ingerly,Pulkit Jain,S. Jaloviar,Robert James,David Jones,J. Jopling,Subhash M. Joshi,C. Kenyon,Huichu Liu,R. McFadden,B. McIntyre,J. Neirynck,C. Parker,L. Pipes,Ian R. Post,S. Pradhan,M. Prince,S. Ramey,T. Reynolds,J. Roesler,J. Sandford,J. Seiple,Pete Smith,Christopher D. Thomas,D. Towner,T. Troeger,Cory E. Weber,P. Yashar,K. Zawadzki,Kaizad Mistry +46 more
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
Kaizad Mistry,C. Allen,C. Auth,B. Beattie,Daniel B. Bergstrom,M. Bost,M. Brazier,M. Buehler,Annalisa Cappellani,R. Chau,C. H. Choi,G. Ding,K. Fischer,Tahir Ghani,R. Grover,W. Han,D. Hanken,M. Hattendorf,J. He,J. Hicks,R. Huessner,D. Ingerly,Pulkit Jain,R. James,L. Jong,Subhash M. Joshi,C. Kenyon,K. Kuhn,K. Lee,Huichu Liu,J. Maiz,B. Mclntyre,P. Moon,J. Neirynck,S. Pae,C. Parker,D. Parsons,Chetan Prasad,L. Pipes,M. Prince,Pushkar Ranade,T. Reynolds,J. Sandford,Lucian Shifren,J. Sebastian,J. Seiple,D. Simon,Swaminathan Sivakumar,Pete Smith,C. Thomas,T. Troeger,P. Vandervoorn,S. Williams,K. Zawadzki +53 more